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MRF89XA Folha de dados(PDF) 72 Page - Microchip Technology

Nome de Peças MRF89XA
Descrição Electrónicos  Ultra Low-Power, Integrated ISM BandSub-GHz Transceiver
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Fabricante Electrônico  MICROCHIP [Microchip Technology]
Página de início  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MRF89XA Folha de dados(HTML) 72 Page - Microchip Technology

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MRF89XA
DS70000622D-page 72
Preliminary
 2010-2017 Microchip Technology Inc.
3.7
Sync Word Recognition
Sync Word recognition (also called as pattern
recognition) is activated by setting the SYNCREN bit
(SYNCREG<5>). The bit synchronizer must be
activated. The block behaves like a shift register; it
continuously compares the incoming data with its
internally programmed Sync Word and asserts the
Sync IRQ source on each occasion that a match is
detected. This is illustrated in Figure 3-15.
During the comparison of the demodulated data, the
first bit received is compared with bit 7 (MSb) of the
byte at address 22 and the last bit received is com-
pared with bit 0 (LSb) of the last byte whose address is
determined by the length of the Sync Word. When the
programmed Sync Word is detected, the user can
assume that this incoming packet is for the node and
can be processed accordingly.
3.7.1
CONFIGURATION
Size: Sync Word size can be set to 8, 16, 24, or 32 bits
through the SYNCWSZ<1:0> bits (SYNCREG<5:4>).
In Packet mode, this field is also used for Sync Word
generation in TX mode.
Error Tolerance: The number of errors tolerated in the
Sync Word recognition can be set to 0, 1, 2, or 3
through the SYNCTEN<1:0> bits (SYNCREG<2:1>).
Value: The Sync Word value is configured in the Sync
Word Parameters in the related Configuration Regis-
ters. In Packet mode, this field is also used for Sync
Word generation in TX mode.
3.7.2
PACKET HANDLER
The packet handler is the block used in Packet mode.
Its functionality is described in Section 3.11, Packet
Mode.
3.7.3
CONTROL
The control block configures and controls the behavior
of the MRF89XA according to the settings programmed
in the configuration registers.
3.7.4
SYNC REGISTERS
The registers associated with SYNC are:
• GCONREG (Register 2-1)
•DMODREG (Register 2-2)
•FDEVREG (Register 2-3)
• BRSREG (Register 2-4)
•FLTHREG (Register 2-5)
• FIFOCREG (Register 2-6)
• FTXRXIREG (Register 2-14)
• FTPRIREG (Register 2-15)
•RSTHIREG (Register 2-16)
• FILCREG (Register 2-17)
•PFCREG (Register 2-18)
• SYNCREG (Register 2-19)
• RSTSREG (Register 2-21)
• OOKCREG (Register 2-22)
• SYNCV31REG (Register 2-23)
• SYNCV23REG (Register 2-24)
FIGURE 3-15:
SYNC WORD RECOGNITION
RX DATA
(NRZ)
DCLK
Bit N-x =
SSYNCVAL<x>
Bit N-1 =
SYNCVAL<0>
SYNC
SYNCVAL<0>
Bit N =


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