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SLG46531 Folha de dados(PDF) 81 Page - Dialog Semiconductor |
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SLG46531 Folha de dados(HTML) 81 Page - Dialog Semiconductor |
81 / 170 page SLG46531_DS_109 Page 80 of 169 SLG46531 9.8.3 4-Bit LUT or 16-Bit Counter / Delay Macrocells Used as 16-Bit Counter / Delay Register Settings Table 77. CNT/DLY0 Register Settings Signal Function Register Bit Address Register Definition LUT4_0 or Counter0 Select reg<1193> 0: LUT4_0 1: Counter0 Delay0 Mode Select or asynchronous counter reset reg<1313:1312> 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level reset Counter/delay0 Clock Source Select reg<1316:1314> 000: Internal OSC clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: 25 MHz OSC clock 110: External Clock 111: Counter6 Overflow CNT0/FSM0's Q are Set to data or Reset to 0s Selection reg<1317> 0: Reset to 0s 1: Set to data (Reg<1583:1576, 1591:1584>) Counter/delay0 Mode Selection reg<1319:1318> 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Counter/delay0 Control Data reg<1591:1576> 1 - 16384 (Delay Time = [Counter Control Data + 1] / Freq) Table 78. CNT/DLY1 Register Settings Signal Function Register Bit Address Register Definition LUT4_1 or Counter1 Select reg<1192> 0: LUT4_1 1: Counter1 Delay1 Mode Select or asynchronous counter reset reg<1321:1320> 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level reset Counter/delay1 Clock Source Select reg<1324:1322> 000: Internal OSC clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: 25MHz OSC clock 110: External Clock 111: Counter0 Overflow CNT0/FSM0's Q are Set to data or Reset to 0s Selection reg<1325> 0: Reset to 0s 1: Set to data (Reg<1599:1592, 1607:1600>) Counter/delay1 Mode Selection reg<1327:1326> 00: Delay mode 01: One Shot 10: Freq. Detect 11: Counter mode Counter/delay1 Control Data reg<1607:1592> 1 - 16384 (Delay Time = [Counter Control Data + 1] / Freq) |
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