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SLG46534 Folha de dados(PDF) 45 Page - Dialog Semiconductor

Nome de Peças SLG46534
Descrição Electrónicos  GreenPAK Programmable Mixed-signal Matrix with Asynchronous State Machine
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SLG46534
9.0 Combination Function Macrocells
The SLG46534 has seventeen combination function macrocells that can serve more than one logic or timing function. In each
case, they can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that
can be implemented in these macrocells:
Three macrocells that can serve as either 2-bit LUTs or as D Flip Flops;
Five macrocells that can serve as either 3-bit LUTs or as D Flip Flops with Set/Reset Input;
One macrocell that can serve as either 3-bit LUT or as Pipe Delay;
One macrocell that can serve as either 2-bit LUT or as Programmable Pattern Generator (PGEN);
Five macrocells that can serve as either 3-bit LUTs or as 8-Bit Counter / Delays;
Two macrocells that can serve as either 4-bit LUTs or as 16-Bit Counter / Delays.
Inputs/Outputs for the 17 combination function macrocells are configured from the connection matrix with specific logic functions
being defined by the state of NVM bits.
When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined
function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
9.1 2-Bit LUT or D Flip Flop Macrocells
There are three macrocells that can serve as either 2-bit LUTs or as D Flip Flops. When used to implement LUT functions, the
2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the
connection matrix. When used to implement D Flip Flop function, the two input signals from the connection matrix go to the data
(D) and clock (clk) inputs for the Flip Flop, with the output going back to the connection matrix.
The operation of the D Flip-Flop and Latch will follow the functional descriptions below:
DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change.
Latch: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is
High)
Figure 10. 2-bit LUT0 or DFF0
DFF0
clk
D
2-bit LUT0 OUT
IN0
IN1
To Connection Matrix
Input <8>
4-bits NVM
From Connection Matrix Output <61>
1-bit NVM
reg <1207:1204>
reg <1191>
From Connection Matrix Output <60>
Q/nQ
reg <1207> DFF or Latch Select
reg <1206> Output Select (Q or nQ)
reg <1205> DFF Initial Polarity Select
LUT Truth
Table
DFF
Registers
S0
S1
S0
S1
S0
S1
0: 2-bit LUT0 IN0
1: DFF0 clk
0: 2-bit LUT0 IN1
1: DFF0 Data
0: 2-bit LUT0 OUT
1: DFF0 OUT


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