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SLG46534 Folha de dados(PDF) 72 Page - Dialog Semiconductor

Nome de Peças SLG46534
Descrição Electrónicos  GreenPAK Programmable Mixed-signal Matrix with Asynchronous State Machine
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SLG46534
9.7 4-Bit LUT or 16-Bit Counter / Delay Macrocells
There are two macrocells that can serve as either 4-bit LUTs or as 16-bit Counter / Delays. When used to implement LUT function,
the 4-bit LUT takes in four input signals from the Connection Matrix and produces a single output, which goes back into the
Connection Matrix. When used to implement 16-Bit Counter / Delay function, four input signals from the connection matrix go to
the external clock (ext_clk), reset (DLY_in/CNT_Reset), Keep and Up for the counter/delay, with the output going back to the
connection matrix.
These two macrocells have an optional Finite State Machine (FSM) function. There are two matrix inputs for Up and Keep to
support FSM functionality. Any counter within Green PAK is counting down by default. In FSM mode (CNT/DLY0 and CNT/DLY1)
it is possible to reverse counting by applying High level to Up input. Also, there is a possibility to pause counting by applying High
level to Keep input, after the level goes Low, the counter will proceed counting.
These macrocells can also operate in a one-shot mode, which will generate an output pulse of user-defined width.
These macrocells can also operate in a frequency detection.
Delay time and Output Period can be calculated using the following formulas:
• Delay time: [(Counter data + 2) / CLK input frequency – Offset*];
• Output Period: [(Counter data + 1) / CLK input frequency – Offset*].
One Shot pulse width can be calculated using formula:
• Pulse width = [(Counter Data + 2) / CLK input frequency – Offset*];
*Offset is the asynchronous time offset between the input signal and the first clock pulse.
For timing diagrams refer to section 9.8 CNT/DLY/FSM Timing Diagrams.
Both of these macrocells can have their active count value read via I2C. See Section 19.5.1.2 Reading Counter Data via I2C for
further details.


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