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CY7C1648KV18 Folha de dados(PDF) 9 Page - Cypress Semiconductor

Nome de Peças CY7C1648KV18
Descrição Electrónicos  144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
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Fabricante Electrônico  CYPRESS [Cypress Semiconductor]
Página de início  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1648KV18 Folha de dados(HTML) 9 Page - Cypress Semiconductor

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Document Number: 001-44061 Rev. *L
Page 9 of 29
CY7C1648KV18
CY7C1650KV18
Write Cycle Descriptions
The write cycle description table for CY7C1650KV18 follows. [10, 11]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L–H
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
H
L–H
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
H
H
H
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
L
H
H
L–H
During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H
L
H
H
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H
H
L
H
L–H
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
H
L
H
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
H
H
L
L–H
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
L
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
H
L–H
No data is written into the device during this portion of a write operation.
H
H
H
H
L–H No data is written into the device during this portion of a write operation.
Notes
10. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
represents rising edge.
11. Is based on a write cycle that was initiated in accordance with the Truth Table on page 8. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a
write cycle, as long as the setup and hold requirements are achieved.


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