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GS1510 Folha de dados(PDF) 5 Page - Gennum Corporation |
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GS1510 Folha de dados(HTML) 5 Page - Gennum Corporation |
5 / 11 page GENNUM CORPORATION 522 - 47 - 00 5 13 TRS_INS Non- synchronous Input Control Signal Input. Used to enable or disable re-insertion of the TRS into the data stream. When TRS_INS is high, the device re-inserts TRS into the incoming data stream based on the internal calculation. The original TRS packets are set to the blanking levels. If the flywheel is enabled, TRS calculated by the flywheel is used for insertion. When TRS_INS is low, the device will not re-insert TRS even if errors in TRS signals are detected. 15 LN_INS Non- synchronous Input Control Signal Input. Used to enable or disable re-insertion of the line number into the data stream. When LN_INS is high, the device re-inserts the line number into the incoming data stream based on the internal calculation. The original line number packets are set to the blanking levels. If the flywheel is enabled, the line number calculated by the flywheel is used for insertion. When LN_INS is low, the device will not re-insert the line number. 16 CRC_INS Non- synchronous Input Control Signal Input. Used to enable or disable re-insertion of the CRC into the data stream. When CRC_INS is high, the device is enabled to re-insert line CRCs based on the internal calculation. When CRC_INS is low, the device will not re-insert the CRCs. 17 FAST_LOCK Synchronous wrt PCLK_IN Input Control Signal Input. Used to control the flywheel synchronization when a switch line occurs. When a low to high transition occurs on the FAST_LOCK signal, the internal flywheel will immediately re-synchronize to the next valid EAV or SAV TRS in the incoming data stream. See Fig. 5 for timing information. 18 RESET Non- synchronous Input Control Signal Input. Used to reset the system state registers to their default 720p parameters. When RESET is high, the fly wheel, TRS Detection, and ANC Detection operate normally. When RESET is low, the flywheel, TRS Detection, and ANC Detection are reset to the 720p parameters after a rising edge on PCLK_IN. The read and write counters are not affected. 21 H Synchronous wrt PCLK_IN Output Control Signal Input. This signal indicates the Horizontal blanking period of the video signal. Refer to Fig. 2 for timing information of H relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and CHROMA respectively. 22 V Synchronous wrt PCLK_IN Output Control Signal Input. This signal indicates the Vertical blanking period of the video signal. Refer to Fig. 2 for timing information of V relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and CHROMA respectively. 23 F Synchronous wrt PCLK_IN Output Control Signal Input. This signal indicates the ODD/EVEN field of the video signal. Refer to Fig. 2 for timing information of F relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and CHROMA respectively. When locked and the input signal is of a progressive scan nature, F stays low at all times. 26,27,71-77,80, 83-89 NC N/A N/A No Connect. Do not connect these pins. 28, 29, 30, 31 VD_STD[3:0] Synchronous wrt PCLK_IN Output Control Signal Output. VD_STD[3:0] indicates which input video standard the device has detected. The GS1510 will indicate all of the formats in SMPTE292M (see Table 1) plus it will indicate an unknown interlace or progressive scan format. PIN DESCRIPTIONS NUMBER SYMBOL TIMING TYPE DESCRIPTION |
Nº de peça semelhante - GS1510 |
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Descrição semelhante - GS1510 |
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