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LTM4676A Folha de dados(PDF) 54 Page - Linear Technology

Nome de Peças LTM4676A
Descrição Electrónicos  Dual 13A or Single 26A 關Module Regulator with Digital Power System Management
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Fabricante Electrônico  LINER [Linear Technology]
Página de início  http://www.linear.com
Logo LINER - Linear Technology

LTM4676A Folha de dados(HTML) 54 Page - Linear Technology

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LTM4676A
54
4676afa
For more information www.linear.com/LTM4676A
applicaTions inForMaTion
MINIMUM ON-TIME CONSIDERATIONS
Minimum on-time, tON(MIN), is the smallest time dura-
tion that the LTM4676A is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
VOUTn
VINn • fOSC
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
Theminimumon-timefortheLTM4676Ais45ns,nominal,
guardband to 90ns.
VARIABLE DELAY TIME, SOFT-START AND OUTPUT
VOLTAGE RAMPING
The LTM4676A must enter its run state prior to soft-start.
The RUNn pins are released after the part initializes and
SVIN is greater than the VIN_ON threshold. If multiple
LTM4676As are used in an application, they should be
configured to share the same RUNn pins. They all hold
their respective RUNn pins low until all devices initialize
and SVIN exceeds the VIN_ON threshold for all devices.
The SHARE_CLK pin assures all the devices connected to
the signal use the same time base.
After the RUNn pin releases, the controller waits for the
user-specified turn-on delay (TON_DELAYn) prior to ini-
tiating an output voltage ramp. Multiple LTM4676As and
other LTC parts can be configured to start with variable
delay times. To work correctly, all devices use the same
timing clock (SHARE_CLK) and all devices must share
the RUNn pin. This allows the relative delay of all parts to
be synchronized. The actual variation in the delay will be
dependent on the highest clock rate of the devices con-
nected to the SHARE_CLK pin (all Linear Technology ICs
are configured to allow the fastest SHARE_CLK signal to
control the timing of all devices). The SHARE_CLK signal
can be ±7.5% in frequency, thus the actual time delays
will have some variance.
Soft-start is performed by actively regulating the load
voltage while digitally ramping the target voltage from 0V
to the commanded voltage set point. The rise time of the
voltage ramp can be programmed using the TON_RISEn
command to minimize inrush currents associated with the
start-up voltage ramp. The soft-start feature is disabled
by setting TON_RISEn to any value less than 0.250ms.
The LTM4676A performs the necessary math internally to
assure the voltage ramp is controlled to the desired slope.
However, the voltage slope can not be any faster than the
fundamentallimitsofthepowerstage.Thenumberofsteps
in the ramp is equal to TON_RISE/0.1ms. Therefore, the
shorter the TON_RISEn time setting, the more jagged the
soft-start ramp appears.
The LTM4676A PWM always operates in discontinuous
mode during the TON_RISEn operation. In discontinuous
mode, the bottom MOSFET (MBn) is turned off as soon
as reverse current is detected in the inductor. This allows
the regulator to start up into a pre-biased load.
There is no analog tracking feature in the LTM4676A; how-
ever, two outputs can be given the same TON_RISEn and
TON_DELAYn times to achieve ratiometric rail tracking.
Because the RUNn pins are released at the same time and
both units use the same time base (SHARE_CLK), the
outputs track very closely. If the circuit is in a PolyPhase
configuration, all timing parameters must be the same.
Table 8. Recommended MFR_IIN_OFFSETn Setting vs
Switching Frequency Setting
SWITCHING
FREQUENCY
(kHz)
FREQUENCY_
SWITCH
COMMAND
VALUE (HEX.)
RECOMMENDED
MFR_IIN_
OFFSETn
SETTING (mA)
RECOMMENDED
MFR_IIN_
OFFSETn
SETTING (HEX.)
250
0xF3E8
20.3
0x8A99
350
0xFABC
24.4
0x8B20
425
0xFB52
27.4
0x8B82
500
0xFBE8
30.5
0x8BE7
575
0x023F
33.6
0x9227
650
0x028A
36.7
0x9259
750
0x02EE
40.8
0x929C
1000
0x03E8
51.0
0x9344
Sync. to
External Clock,
fSYNC
N/A
0.041 • fSYNC +
10.037
*
*See Appendix C: PMBus Command Details, L11 data format.


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