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FAN3213 Folha de dados(PDF) 12 Page - ON Semiconductor |
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FAN3213 Folha de dados(HTML) 12 Page - ON Semiconductor |
12 / 19 page www.onsemi.com 12 Applications Information Input Thresholds The FAN3213 and the FAN3214 drivers consist of tw o identical channels that may be used independently at rated current or connected in parallel to double the individual current capacity. The input thresholds meet industry-standard TTL- logic thresholds independent of the V DD voltage, and there is a hysteresis voltage of approximately 0.4 V. These levels per mit the inputs to be driven from a range of input logic s ignal levels for w hich a voltage over 2 V is considered logic HIGH. The driving signal for the TTL inputs should have fast rising and falling edges w ith a slew rate of 6 V/µs or faster, so a rise time from 0 to 3.3 V should be 550 ns or less. With reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the dr iver input, causing erratic operation. Static Supply Current In the IDD (static) typical performance characteristics show n in Figure 8 and Figur e 9, each curve is produced w ith both inputs floating and both outputs LOW to indicate the low est static IDD current. For other states, additional current flow s through the 100 k resistors on the inputs and outputs show n in the block diagram of each part (see Figure 4 and Figure 5). In these cases, the actual static IDD current is the value obtained from the curves plus this additional current. MillerDrive™ Gate Drive Technology FA N3213 and FA N3214 gate drivers incorporate the Miller Drive™ architecture show n in Figure 28. For the output stage, a combination of bipolar and MOS devices provide large currents over a w ide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT sw ings betw een 1/3 to 2/3 VDD and the MOS devices pull the output to the HIGH or LOW rail. The purp ose of the Miller Drive™ architecture is to speed up sw itching by providing high current during the Miller plateau region w hen the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. For applications w ith zero voltage sw itching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast sw itching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is sw itched ON. The output pin slew rate is determined by V DD voltage and the load on the output. It is not user adjustable, but a series resistor can be added if a slow er rise or fall time at the MOSFET gate is needed. Input stage V DD V OUT Figure 28. MillerDrive™ Output Architecture Under-Voltage Lockout The FAN321x startup logic is optimized to drive ground- referenced N-channel MOSFETs w ith an under-voltage lockout ( UVLO) function to ensure that the IC starts up in an orderly fashion. When V DD is rising, yet below the 3.9 V operational level, this circuit holds the output LOW, regardless of the status of the input pins. After the part is active, the supply voltage must drop 0.2 V before the part shuts dow n. This hysteresis helps prevent chatter w hen low VDD supply voltages have noise from the pow er sw itching. This configuration is not suitable for driving high-side P-channel MOSFETs because the low output voltage of the driver w ould turn the P-channel MOSFET on w ith VDD below 3.9 V. VDD Bypass Capacitor Guidelines To enable this IC to turn a device ON quickly, a local high-frequency bypass capacitor, CBYP, w ith low ESR and ESL should be connected betw een the VDD and GND pins w ith minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10 µF to 47 µF commonly found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the V DD supply to ≤ 5%. This is often achieved w ith a value ≥ 20 times the equivalent load capacitance CEQV, defined here as QGATE/VDD. Ceramic capacitors of 0.1 µF to 1 µF or larger are common choices, as are dielectrics, such as X5R and X7R, w ith good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, the value of CBYP may be increased, to 50-100 times the CEQV, or CBYP may be split into tw o capacitors. One should be a larger value, based on equivalent load capacitance, and the other a s maller value, such as 1-10 nF mounted closest to the VDD and GND pins to carry the higher - frequency components of the current pulses. The bypass capacitor must provide the pulsed current from both of the driver channels and, if the drivers are sw itching simultaneously, the combined peak current sourced from the CBYP w ould be tw ice as large as w hen a single channel is sw itching. |
Nº de peça semelhante - FAN3213 |
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Descrição semelhante - FAN3213 |
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