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AD5390BCP-5 Folha de dados(PDF) 8 Page - Analog Devices |
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AD5390BCP-5 Folha de dados(HTML) 8 Page - Analog Devices |
8 / 40 page AD5382 Rev. 0 | Page 8 of 40 TIMING CHARACTERISTICS SPI, QSPI, MICROWIRE, OR DSP COMPATIBLE SERIAL INTERFACE Table 6. DVDD= 2.7 V to 5.5 V ; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min SYNC falling edge to SCLK falling edge setup time t5 4 13 ns min 24th SCLK falling edge to SYNC falling edge t6 4 33 ns min Minimum SYNC low time t7 10 ns min Minimum SYNC high time t7A 50 ns min Minimum SYNC high time in Readback mode t8 5 ns min Data setup time t9 4.5 ns min Data hold time t104 30 ns max 24th SCLK falling edge to BUSY falling edge t11 670 ns max BUSY pulse width low (single channel update) t12 4 20 ns min 24th SCLK falling edge to LDAC falling edge t13 20 ns min LDAC pulse width low t14 100 ns max BUSY rising edge to DAC output response time t15 0 ns min BUSY rising edge to LDAC falling edge t16 100 ns min LDAC falling edge to DAC output response time t17 8 µs typ DAC output settling time t18 20 ns min CLR pulse width low t19 35 µs max CLR pulse activation time t20 5 20 ns max SCLK rising edge to SDO valid t215 5 ns min SCLK falling edge to SYNC rising edge t225 8 ns min SYNC rising edge to SCLK rising edge t23 20 ns min SYNC rising edge to LDAC falling edge 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and are timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, Figure 4, and Figure 5. 4 Standalone mode only. 5 Daisy-chain mode only. CL 50pF TO OUTPUT PIN VOH (MIN) OR VOL (MAX) 200 µA 200 µA IOL IOH Figure 2. Load Circuit for SDO Timing Diagram (Serial Interface, Daisy-Chain Mode) |
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Descrição semelhante - AD5390BCP-5 |
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