REV. 0

AD5231

–6–

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

CLK

SDI

SDO

GND

T

RDY

CS

PR

WP

A

W

AD5231

O1

B

O2

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Description

1

O1

2

CLK

Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.

3

SDI

Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.

4

SDO

Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 and 10

activate the SDO output. (See Instruction operation Truth Table, Table III.) Other commands shift out

the previously loaded SDI bit pattern delayed by 24 clock pulses. This allows daisy-chain operation of

multiple packages.

5

GND

Ground Pin, Logic Ground Reference

Negative Supply. Connect to zero volts for single supply applications.

7T

8

B

B Terminal of RDAC

9W

10

A

A Terminal of RDAC1

11

Positive Power Supply Pin

12

WP

Write Protect Pin. When active low,

WP prevents any changes to the present contents except PR and

cmd 1 and 8 will refresh the RDAC register from EEMEM. Execute on NOP instruction before returning

to

WP high.

13

PR

Hardware Override Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM

activated at the logic high transition).

14

CS

Serial Register Chip Select Active Low. Serial register operation takes place when

CS returns to logic high.

15

RDY

Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10, and

PR.

16

O2