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MAX8725ETI Folha de dados(PDF) 29 Page - Maxim Integrated Products |
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MAX8725ETI Folha de dados(HTML) 29 Page - Maxim Integrated Products |
29 / 30 page Multichemistry Battery Chargers with Automatic System Power Selector ______________________________________________________________________________________ 29 e) Connect C1 and C2 to the high-side MOSFET (10mm max length). Return these capacitors to the power ground plane. f) Minimize the LX node (MOSFETs, rectifier cath- ode, inductor (15mm max length)). Ideally, surface-mount power components are flush against one another with their ground terminals almost touching. These high-current grounds are then connected to each other with a wide, filled zone of top-layer copper, so they do not go through vias. The resulting top-layer ground plane is connected to the normal inner-layer ground plane at the out- put ground terminals, which ensures that the IC’s analog ground is sensing at the supply’s output terminals without interference from IR drops and ground noise. Other high-current paths should also be minimized, but focusing primarily on short ground and current-sense connections eliminates about 90% of all PC board layout problems. 2) Place the IC and signal components. Keep the main switching node (LX node) away from sensitive ana- log components (current-sense traces and REF capacitor). Important: the IC should be less than 10mm from the current-sense resistors. Quiet connections to REF, VCTL, ICTL, CCV, CCI, CCS, IINP, ACIN, and DCIN should be returned to a separate ground (GND) island. The appropriate traces are marked on the schematic with the ground symbol ( ). There is very little current flow- ing in these traces, so the ground island need not be very large. When placed on an inner layer, a siz- able ground island can help simplify the layout because the low-current connections can be made through vias. The ground pad on the backside of the package should also be connected to this quiet ground island. 3) Keep the gate drive traces (DHI and DLO) as short as possible (L < 20mm), and route them away from the current-sense lines and REF. These traces should also be relatively wide (W > 1.25mm). 4) Place ceramic bypass capacitors close to the IC. The bulk capacitors can be placed further away. 5) Use a single-point star ground placed directly below the part at the PGND pin. Connect the power ground (ground plane) and the quiet ground island at this location. See Figure 12. Chip Information TRANSISTOR COUNT: 2720 PROCESS: BiCMOS INDUCTOR CIN COUT COUT INPUT OUTPUT KELVIN-SENSE VIAS UNDER THE SENSE RESISTOR (REFER TO EVALUATION KIT) GND PGND POWER PATH QUIET GROUND ISLAND Figure 12. PC Board Layout Examples |
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