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UPD78F9026A Folha de dados(PDF) 90 Page - NEC |
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UPD78F9026A Folha de dados(HTML) 90 Page - NEC |
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90 / 213 page  CHAPTER 5 CLOCK GENERATION CIRCUIT User's Manual U11919EJ3V0UM00 90 5.5 Operation of Clock Generation Circuit The clock generation circuit generates the following clocks and controls operation modes of the CPU, such as the standby mode: • System clock fX • CPU clock fCPU • Clock to peripheral hardware The operation of the clock generation circuit is determined by the processor clock control register (PCC), as follows: (a) The slow mode 2 fCPU (1.6 µs: at 5.0-MHz operation) of the system clock is selected when the RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is stopped . (b) Two types of CPU clocks fCPU (0.2 µs and 0.8 µs: at 5.0-MHz operation) can be selected by the PCC setting. (c) Two standby modes, STOP and HALT, can be used. (d) The clock to the peripheral hardware is supplied by dividing the system clock. The other peripheral hardware is stopped when the system clock is stopped (except, however, the external clock input operation). |
Nº de peça semelhante - UPD78F9026A |
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Descrição semelhante - UPD78F9026A |
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