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TMP141AIDBVR Folha de dados(PDF) 8 Page - Texas Instruments |
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TMP141AIDBVR Folha de dados(HTML) 8 Page - Texas Instruments |
8 / 19 page TMP141 SBAS347 − MARCH 2005 www.ti.com 8 DIGITAL INTERFACE Up to four TMP141 devices can be connected to a single signaling line, which is called Single-Wire Data (SWD). This line is similar to the data line (SMBDAT) of the industry-standard SMBus. The SensorPath bus uses a power supply of 3.3V; therefore, the signaling levels are approximately 3.3V and 0V. Data is encoded in a pulse width encoding scheme. All signaling is done by pulling the bus low for varying lengths of time. With the exception of Reset and Attention Request, the master starts all bits. Thus, when sending data, the TMP141 does not pull the bus low. Rather, when the TMP141 needs to send a ‘1’, it first detects that the line has been pulled low by the master, and then holds the line low long enough to signal a ‘1’. To send a ‘0’, the TMP141 simply leaves the bus alone; the master has already placed a ‘0’ on the bus. The SWD interface used on the TMP141 has five types of signals that are identified by the length of time that the line is held low. Conceptually, this device operates as a five-state signaling system. The more common signals have shorter durations in order to speed overall transmission. The five signals and their approximate times are: D Data 0: Transmit a ‘0’ bit (15µs) D Data 1: Transmit a ‘1’ bit (42µs) D Start: Used by the master at the beginning of a transaction (95 µs) D Attention Request: May be used by the TMP141 to request service (196 µs) D Reset: Must be asserted by both the master and slave(s) after power up. It may be asserted at other times as needed (at least 348 µs). The bus must be inactive for at least 11 µs before any signal. Start All devices on the bus continuously monitor the bus. The master also monitors the bus to verify that it is inactive before issuing a Start Bit. During the Start Bit, both the master and slave(s) monitor the bus to detect an Attention Request or a Reset. If there is an Attention Request, or a Reset, the current signal is not treated as a Start Bit. The master may reissue the Start Bit at a later time, but is not required to. Attention Request Any slave device may signal an Attention Request. Before sending an Attention Request, the slave monitors the bus to ensure that it is inactive. If an Attention Request coincides with a data bit from another device or a Start Bit from the master, the Attention Request will take precedence since the Attention Request signal holds the bus low longer. The master and all communicating slaves will monitor the bus to detect an Attention Request. The master monitors the bus in order to allow resending, in case the Attention Request started simultaneously with a Start Bit or a data bit. If the master was in the midst of a transaction when the Attention Request was asserted, the master can either continue with the transaction by repeating the bit that was extended by the Attention Request, initiating the next bit if a bit was not extended, or it can service the Attention Request by issuing a new start command for a new transaction. Power-On Reset All devices on the SWD bus, including the TMP141, are required to generate a Reset signal at power up. Reset aborts any operation in progress, and sets all registers to the default values. The device that holds SWD low the longest will define how long the Reset lasts. After a Reset, a slave device may not send an Attention Request until the master has sent at least 14 bits of data on the SWD bus. Device Reset The TMP141 will also Reset when the Reset bit is written to the Device Control Register (bit 0). All registers are set to the default value. The two least significant bits of the Device Control Register are the only locations that respond to a broadcast write command from the master. A software-programmed reset of a device by writing to its Device Control Register will not cause a Reset signal on the bus. BUS RESET A Bus Reset occurs when the TMP141 detects a Reset signal on the SWD bus. Upon Bus Reset, the TMP141 will abandon any communication in progress. Internal registers are not reset to their power-up values; thus, any error flags such as BER or ORUN will remain unaffected. If a conversion was in progress, it will continue to completion. |
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