WS7810QM

Will Semiconductor Ltd.

10

Aug, 2017_V1.3

10 = Low power (low power)

11 = Reserved

Trigger_Mask_2

Bit[5]:

If this bit is set, trigger 2 is disabled. When all

triggers are disabled, if writing to a register

that is associated with trigger 2, the data

goes directly to the destination register.

0

Trigger_Mask_1

Bit[4]:

If this bit is set, trigger 1 is disabled. When all

triggers are disabled, if writing to a register

that is associated with trigger 1, the data

goes directly to the destination register.

0

Trigger_Mask_0

Bit[3]:

If this bit is set, trigger 0 is disabled. When all

triggers are disabled, if writing to a register

that is associated with trigger 0, the data

goes directly to the destination register.

0

Trigger_2

Bit[2]:

If this bit is set, data is loaded into the trigger

2 registers.

0

Trigger_1

Bit[1]:

If this bit is set, data is loaded into the trigger

1 registers.

0

Trigger_0

Bit[0]:

If this bit is set, data is loaded into the trigger

0 registers.

0

PRODUCT_ID

001D

PRODUCT_ID

Bits[7:0]:

This is a read-only register. However, during

the programming of the Unique Slave

Identifier (USID), a write command sequence

is performed on this register but the value is

not changed.

00001010

MANUFAC-

TURER_ID

001E

MANUFACTURER_ID

Bits[7:0]:

Read-only register

10111100

MAN_USID

001F

Reserved

Bits[7:6]:

Reserved

00

MANUFACTURER_ID

Bits[5:4]:

Read-only register

11

USID

Bits[3:0]:

Programmable USID. A write to these bits

programs the USID.

1010

Note 3: Unlike the complete independence between triggers 0, 1, and 2, and also between the associated trigger masks 0, 1, and 2,

respectively, as described in the MIPI RFFE Specification this device uses additional interactions between the provided trigger functions.

The delayed application of updated data to all triggerable registers in this device may be accomplished using any of the three triggers (0,

1, or 2), provided that the particular triggerable used is not currently masked off. If multiple triggers are enabled, any or all of those are

sufficient to cause the data to be transferred from shadow registers to destination registers for all triggerable registers in the device.

It is also necessary to disable all three triggers (i.e., set all three trigger masks) to ensure that data written to any triggerable register will

immediately be written to the destination register at the conclusion of the RFFE command sequence where the data is written.