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High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
P 6
LOW Vcc DATA RETENTION WAVEFORM(1) ( /CE Controlled )
LOW Vcc DATA RETENTION WAVEFORM(2) ( CE2 Controlled )
KEY TO SWITCHING WAVEFORMS
WAFEFORM
INPUTS
OUTPUTS
Must be standby
Must be standby
May change for H to L
Will be change from H to L
May change for L to H
May change for L to H
Don’t care any change permitted
Change state unknown
Does not apply
Center line is high impedance “OFF” state
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
Input Rise and Fall Times
5ns
Input and Output
Timing Reference Level
0.5Vcc