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GD25B64C Folha de dados(PDF) 20 Page - GigaDevice Semiconductor (Beijing) Inc.

Nome de Peças GD25B64C
Descrição Electrónicos  3.3V Uniform Sector Dual and Quad Serial Flash
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Fabricante Electrônico  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Página de início  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25B64C Folha de dados(HTML) 20 Page - GigaDevice Semiconductor (Beijing) Inc.

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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B64C
20
7.9.
Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1
and IO0. The command sequence is shown in followed Figure 9. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
Figure 9. Quad Output Fast Read Sequence Diagram
7.10.
Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input
the 3-byte address (A23-
0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in
during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The
command sequence is shown in followed Figure10. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Dual I/O Fast Read with
“Continuous Read Mode”
The Dual I/O Fast Read command
can further reduce command overhead through setting the “Continuous Read
Mode” bits (M7-4) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next
Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The
command sequence is shown in followed Figure11.
If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next
command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset
command can be used to reset (M5-4) before issuing normal command.
Command
0
1
2
3
4
5
6
7
6BH
CS#
SCLK
IO0
IO1
High-Z
8
9 10
28 29 30 31
3
2
1
0
23 22 21
24-bit address
34 35 36 37
33
1
5
1
5
1
5
1
38 39
Byte1
32
42 43 44 45
41
46 47
40
5
Dummy Clocks
0
4
0
4
0
4
0
4
4
5
IO2
High-Z
IO3
High-Z
CS#
SCLK
IO0
IO1
2
6
2
6
2
6
2
6
6
3
7
3
7
3
7
3
7
7
Byte2 Byte3 Byte4
IO2
IO3


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