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8XC152JB Folha de dados(PDF) 4 Page - Intel Corporation |
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8XC152JB Folha de dados(HTML) 4 Page - Intel Corporation |
4 / 17 page 8XC152JAJBJCJD 80C152JBJD General Description The 80C152JBJD is a ROMless extension of the 80C152 Universal Communication controller The 80C152JB has the same five 8-bit IO ports of the 80C152 plus an additional two 8-bit IO ports Port 5 and Port 6 The 80C152JBJD also has two addi- tional control pins EBEN (EPROM Bus ENable) and EPSEN (EPROM bus Program Store ENable) EBEN selects the functionality of Port 5 and Port 6 When EBEN is low these ports are strictly IO simi- lar to Port 4 The SFR location for Port 5 is 91H and Port 6 is 0A1H This means Port 5 and Port 6 are not bit addressable With EBEN low all program memo- ry fetches take place via Port 0 and Port 2 (The 80C152 is a ROMless only product) When EBEN is high Port 5 and Port 6 form an addressdata bus called the E-Bus (EPROM-Bus) for program memory operations EPSEN is used in conjunction with Port 5 and Port 6 program memory operations EPSEN functions like PSEN during program memory operation but sup- ports Port 5 and Port 6 EPSEN is the read strobe to external program memory for Port 5 and Port 6 EPSEN is activated twice during each machine cycle unless an external data memory operation occurs on Port(s) 0 and Port 2 When external data memory is accessed the second activation of EPSEN is skipped which is the same as when using PSEN Note that data memory fetches cannot be made through Ports 5 and 6 When EBEN is high and EA is low all program mem- ory operations take place via Ports 5 and 6 The high byte of the address goes out on Port 6 and the low byte is output on Port 5 ALE is still used to latch the address on Port 5 Next the op code is read on Port 5 The timing is the same as when using Ports 0 and 2 for external program memory operations Table 1 Program Memory Fetches EBEN EA Program PSEN EPSEN Comments Fetch via 0 0 P0 P2 Active Inactive Addresses 0 – 0FFFFH 0 1 NA NA NA Invalid Combination 1 0 P5 P6 Inactive Active Addresses 0 – 0FFFFH 1 1 P5 P6 Inactive Active Addresses 0 – 1FFFH P0 P2 Active Inactive Addresses t 2000H Table 2 8XC152 Product Differences ROMless CSMACD HDLCSDLC ROM PLCC PLCC 5 IO 7 I0 Version and Only Version and Only Ports Ports HDLCSDLC Available DIP 80C152JA (83C152JA) 80C152JB 80C152JC (83C152JC) 80C152JD NOTES e options available 0 standard frequency range 35 MHz to 12 MHz 0‘‘b1’’ frequency range 35 MHz to 165 MHz 4 |
Nº de peça semelhante - 8XC152JB |
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Descrição semelhante - 8XC152JB |
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