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MC100E154 Folha de dados(PDF) 1 Page - ON Semiconductor |
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MC100E154 Folha de dados(HTML) 1 Page - ON Semiconductor |
1 / 4 page D2a D1a D1b LOGIC DIAGRAM SEL LEN1 LEN2 VEE MR D0a D0b 26 27 28 2 3 4 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 5 6 7 8 9 10 D4b D4a D3b D3a VCCO Q4 Q4 Q3 Q3 VCC Q2 Q2 Q1 Q1 D2b VCCO Q0 Q0 D0a D0b D1a D1b D2a D2b D3a D3b D4a D4b SEL LEN1 LEN2 MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 SEL D Q EN R Q D Q EN R Q D Q EN R Q D Q EN R Q D Q EN R Q MUX SEL MUX SEL MUX SEL MUX SEL MUX 1 Pinout: 28-Lead PLCC (Top View) * All VCC and VCCO pins are tied together on the die. MOTOROLA SEMICONDUCTOR TECHNICAL DATA 2–1 REV 2 © Motorola, Inc. 1996 12/93 5Bit 2:1 MuxLatch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. • 850ps Max. LEN to Output • 825ps Max. D to Output • Differential Outputs • Asynchronous Master Reset • Dual Latch-Enables • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors PIN NAMES Pin Function D0a – D4a Input Data a D0b – D4b Input Data b SEL Data Select Input LEN1, LEN2 Latch Enables MR Master Reset Q0 – Q4 True Outputs Q0 – Q4 Inverted Outputs TRUTH TABLE SEL Data H L a b MC10E154 MC100E154 5-BIT 2:1 MUX-LATCH FN SUFFIX PLASTIC PACKAGE CASE 776-02 |
Nº de peça semelhante - MC100E154 |
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Descrição semelhante - MC100E154 |
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