MC10E196 MC100E196

MOTOROLA

ECLinPS and ECLinPS Lite

DL140 — Rev 4

2–4

USING THE FTUNE ANALOG INPUT

The analog FTUNE pin on the E196 device is intended to

enhance the 20 ps resolution capabilities of the fully digital

E195. The level of resolution obtained is dependent on the

number of increments applied to the appropriate range on the

FTUNE pin.

To provide another level of resolution the FTUNE pin must

be capable of adjusting the delay by greater than the 20 ps

digital resolution. From the provided graphs one sees that this

requirement is easily achieved as over the entire FTUNE

voltage range a 100 ps delay can be achieved. This extra

analog range ensures that the FTUNE pin will be capable even

under worst case conditions of covering the digital

resolution.Typically the analog input will be driven by an

external DAC to provide a digital control with very fine analog

output steps. The final resolution of the device will be

dependent on the width of the DAC chosen.

To determine the voltage range necessary for the FTUNE

input, the graphs provided should be used. As an example if a

range of 40 ps is selected to cover worst case conditions and

ensure coverage of the digital range, from the 100E196 graph

a voltage range of –3.25 V to –4.0 V would be necessary on the

FTUNE pin. Obviously there are numerous voltage ranges

which can be used to cover a given delay range, users are

given the flexibility to determine which one best fits their

designs.

Cascading Multiple E196’s

To increase the programmable range of the E195 internal

cascade circuitry has been included. This circuitry allows for

the cascading of multiple E195’s without the need for any

external gating. Furthermore this capability requires only one

more address line per added E195. Obviously cascading

multiple PDC’s will result in a larger programmable range,

however, this increase is at the expense of a longer minimum

delay.

Figure 1 illustrates the interconnect scheme for cascading

two E195’s. As can be seen, this scheme can easily be

expanded for larger E195 chains. The D7 input of the E195 is

the cascade control pin. With the interconnect scheme of

Figure 1 when D7 is asserted it signals the need for a larger

programmable range than is achievable with a single device.

An expansion of the latch section of the block diagram is

pictured below. Use of this diagram will simplify the

explanation of how the cascade circuitry works. When D7 of

chip #1 above is low the cascade output will also be low while

the cascade bar output will be a logical high. In this condition

the SET MIN pin of chip #2 will be asserted and thus all of the

latches of chip #2 will be reset and the device will be set at its

minimum delay. Since the RESET and SET inputs of the

latches are overriding any changes on the A0–A6 address bus

will not affect the operation of chip #2.

Chip #1 on the other hand will have both SET MIN and SET

MAX de-asserted so that its delay will be controlled entirely by

the address bus A0–A6. If the delay needed is greater than

can be achieved with 31.75 gate delays (1111111 on the

A0–A6 address bus) D7 will be asserted to signal the need to

cascade the delay to the next E195 device. When D7 is

asserted the SET MIN pin of chip #2 will be de-asserted and

the delay will be controlled by the A0–A6 address bus. Chip #1

on the other hand will have its SET MAX pin asserted

resulting in the device delay to be independent of the A0–A6

address bus.

When the SET MAX pin of chip #1 is asserted the D0 and D1

latches will be reset while the rest of the latches will be set. In

addition, to maintain monotonicity an additional gate delay is

selected in the cascade circuitry. As a result when D7 of chip

#1 is asserted the delay increases from 31.75 gates to 32

gates. A 32 gate delay is the maximum delay setting for

the E195.

When cascading multiple PDC’s it will prove more cost

effective to use a single E196 for the MSB of the chain while

using E195 for the lower order bits. This is due to the fact that

only one fine tune input is needed to further reduce the delay

step resolution.

ADDRESS BUS (A0–A6)

A7

INPUT

D1

D0

LEN

VEE

IN

IN

VBB

VCC

VCC0

Q

Q

VCC0

D1

D0

LEN

VEE

IN

IN

VBB

VCC

VCC0

Q

Q

VCC0

OUTPUT

E196

Chip #1

E196

Chip #2

Figure 1. Cascading Interconnect Architecture

FTUNE

LINEAR

INPUT

FTUNE