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MC10E446 Folha de dados(PDF) 4 Page - ON Semiconductor |
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MC10E446 Folha de dados(HTML) 4 Page - ON Semiconductor |
4 / 6 page MC10E446 MC100E446 MOTOROLA ECLinPS and ECLinPS Lite DL140 — Rev 4 2–4 Applications Information The MC10E/100E446 is an integrated 4:1 parallel to serial converter. The chip is designed to work with the E445 device to provide both transmission and receiving of a high speed serial data path. The E446 can convert 4 bits of data into a 1.3Gb/s NRZ data stream. The device features a SYNC input which allows the user to reset the internal clock circuitry and restart the conversion sequence (see timing diagram A). The E446 features a differential serial input and internal divide by 8 circuitry to facilitate the cascading of two devices to build a 8:1 multiplexer. Figure 1 illustrates the architecture for a 8:1 multiplexer using two E446’s; the timing diagram for this configuration can be found on the following page. Notice the serial outputs (SOUT) of the lower order converter feed the serial inputs of the the higher order device. This feed through of the serial inputs bounds the upper end of the frequency of operation. The clock to serial output propagation delay plus the setup time of the serial input pins must fit into a single clock period for the cascade architecture to function properly. Using the worst case values for these two parameters from the data sheet, TPD CLK to SOUT = 1480ps and tS for SIN = –200ps, yields a minimum period of 1280ps or a clock frequency of 780MHz. The clock frequency is somewhat lower than that of a single converter, to increase this frequency some games can be played with the clock input of the higher order E446. By delaying the clock feeding E446A relative to the clock of E446B the frequency of operation can be increased. Q3 Q7 Q2 Q6 Q1 Q5 Q0 Q4 SOUT SOUT E446B Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 SIN SIN E446A CLK CLK 1000ps 1600ps 600ps CLOCK Tpd CLK to SOUT Figure 1. Cascaded 8:1 Converter Architecture SOUT SOUT 1000ps Serial Data Parallel Data Timing Diagram B. 8:1 Parallel to Serial Conversion D0–1 D1–1 D2–1 D3–1 D0–2 D1–2 D2–2 D3–2 D0–1 D1–1 D2–1 D3–1 D4–1 D5–1 D6–1 D7–1 CLK RESET D0 D1 D2 D3 SOUT CL/4 CL/8 D4–1 D5–1 D6–1 D7–1 D4–2 D5–2 D6–2 D7–2 D4 (D0B) D5 (D1B) D6 (D2B) D7 (D3B) D0–2 |
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