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MC10EP32 Folha de dados(PDF) 1 Page - ON Semiconductor |
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MC10EP32 Folha de dados(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 1 1 Publication Order Number: MC10EP32/D MC10EP32 B2 Divider The MC10EP32 is an integrated B2 divider. The differential clock inputs and the VBB allow a differential, single–ended or AC coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01 µF capacitor. The reset pin is asynchronous and is asserted on the rising edge. Upon power–up, the internal flip–flops will attain a random state; the reset allows for the synchronization of multiple EP32’s in a system. • 250ps Typical Propagation Delay • 3 GHz Typical Toggle Frequency • PECL mode: 3.0V to 5.5V VCC with VEE = 0V • ECL mode: 0V VCC with VEE = –3.0V to –5.5V • Internal Input Resistors: Pulldown on D, D • Q Output will default LOW with inputs open or at VEE • ESD Protection: >4KV HBM, >200V MM • VBB Output • New Differential Input Common Mode Range • Moisture Sensitivity Level 1, Indefinite Time Out of Drypack • Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34 • Transistor Count = 78 devices 1 2 3 45 6 7 8 Q VEE VCC Figure 1. 8–Lead Pinout (Top View) and Logic Diagram CLK Q CLK VBB RESET R B2 SO–8 D SUFFIX CASE 751 PIN DESCRIPTION PIN CLK, CLK Reset ECL Asynchronous Reset FUNCTION ECL Clock Inputs http://onsemi.com TRUTH TABLE CLK X Z CLK X Z RESET Z L Q L F Q H F Z = LOW to HIGH Transition Z = HIGH to LOW Transition F = Divide by 2 Function VBB Reference Voltage Output Q, Q ECL Data Outputs MARKING DIAGRAM Device Package Shipping ORDERING INFORMATION MC10EP32D SOIC 98 Units/Rail MC10EP32DR2 SOIC 2500 Tape & Reel VCC VEE Negative, 0 Supply Positive Supply ALYW HEP32 1 8 A = Assembly Location L = Wafer Lot Y = Year W = Work Week *For additional information, see Application Note AND8002/D 1 8 |
Nº de peça semelhante - MC10EP32 |
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Descrição semelhante - MC10EP32 |
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