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MC100EP31DR2 Folha de dados(PDF) 1 Page - ON Semiconductor |
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MC100EP31DR2 Folha de dados(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2001 April, 2001 – Rev. 5 1 Publication Order Number: MC10EP31/D MC10EP31, MC100EP31 3.3V / 5VECL D Flip-Flop with Set and Reset The MC10/100EP31 is a D flip–flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance available. Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip–flop when CLK is low and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK. The 100 Series contains temperature compensation. • 340 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: V CC = 3.0 V to 5.5 V with VEE = 0 V • NECL Mode Operating Range: V CC = 0 V with VEE = –3.0 V to –5.5 V • Open Input Default State • Q Output Will Default LOW with Inputs Open or at V EE http://onsemi.com Device Package Shipping ORDERING INFORMATION MC10EP31D SO–8 98 Units/Rail MC10EP31DR2 SO–8 2500 Tape & Reel MC100EP31D SO–8 98 Units/Rail MC100EP31DR2 SO–8 2500 Tape & Reel MC10EP31DT TSSOP–8 100 Units/Rail MC10EP31DTR2 TSSOP–8 2500 Tape & Reel MC100EP31DT TSSOP–8 100 Units/Rail MC100EP31DTR2 TSSOP–8 2500 Tape & Reel L = Wafer Lot Y = Year W = Work Week *For additional information, see Application Note AND8002/D H = MC10 K = MC100 A = Assembly Location SO–8 D SUFFIX CASE 751 MARKING DIAGRAMS* TSSOP–8 DT SUFFIX CASE 948R ALYW KEP31 ALYW HP31 HEP31 ALYW ALYW KP31 1 8 1 8 1 8 1 8 1 8 1 8 |
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