SCL

SDA

t

h(2)

t

(buf)

t

su(2)

t

su(3)

Start

Condition

Stop

Condition

T0028-02

SCL

SDA

t

w(H)

t

w(L)

t

r

t

f

t

su(1)

t

h(1)

T0027-03

7

TAS5441-Q1

www.ti.com

SLOSE41 – APRIL 2020

Product Folder Links: TAS5441-Q1

Submit Documentation Feedback

Copyright © 2020, Texas Instruments Incorporated

(1)

A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of

SCL.

6.6 Timing Requirements for I

over recommended operating conditions (unless otherwise noted)

MIN

NOM

MAX

UNIT

SCL clock frequency

400

kHz

Rise time for both SDA and SCL signals

300

ns

Fall time for both SDA and SCL signals

300

ns

SCL pulse duration, high

0.6

µs

SCL pulse duration, low

1.3

µs

Setup time for START condition

0.6

µs

START condition hold time before generation of first clock pulse

0.6

µs

Data setup time

100

ns

Data hold time

ns

Setup time for STOP condition

0.6

µs

Load capacitance for each bus line

400

pF

Figure 1. SCL and SDA Timing

Figure 2. Timing for Start and Stop Conditions