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TAS5441-Q1 Folha de dados(PDF) 7 Page - Texas Instruments |
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TAS5441-Q1 Folha de dados(HTML) 7 Page - Texas Instruments |
7 / 28 page SCL SDA t h(2) t (buf) t su(2) t su(3) Start Condition Stop Condition T0028-02 SCL SDA t w(H) t w(L) t r t f t su(1) t h(1) T0027-03 7 TAS5441-Q1 www.ti.com SLOSE41 – APRIL 2020 Product Folder Links: TAS5441-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. 6.6 Timing Requirements for I 2C Interface Signals over recommended operating conditions (unless otherwise noted) MIN NOM MAX UNIT f(SCL) SCL clock frequency 400 kHz tr Rise time for both SDA and SCL signals 300 ns tf Fall time for both SDA and SCL signals 300 ns tw(H) SCL pulse duration, high 0.6 µs tw(L) SCL pulse duration, low 1.3 µs tsu(2) Setup time for START condition 0.6 µs th(2) START condition hold time before generation of first clock pulse 0.6 µs tsu(1) Data setup time 100 ns th(1) Data hold time 0(1) ns tsu(3) Setup time for STOP condition 0.6 µs C(B) Load capacitance for each bus line 400 pF Figure 1. SCL and SDA Timing Figure 2. Timing for Start and Stop Conditions |
Nº de peça semelhante - TAS5441-Q1 |
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Descrição semelhante - TAS5441-Q1 |
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