7-847

CD4034BMS

FIGURE 11. REGISTER STAGE LOGIC DIAGRAM (1 OF 8 STAGES)

TRUTH TABLE REGISTER INPUT-LEVELS AND

RESULTING REGISTER OPERATION

“A”

ENABLE

P/S

A/B

A/S

OPERATION*

0

0

0

X

Serial Mode; Synch. Serial Data Input, “A” Parallel Data Outputs Disabled

0

0

1

X

Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output

0

1

0

0

Parallel Mode; “B” Synch. Parallel Data Inputs, “A” Parallel Data Outputs Disabled

0

1

0

1

Parallel Mode; “B” Asynch. Parallel Data Inputs, “A” Parallel Data Outputs Disabled

0

1

1

0

Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs, Synch. Data

Recirculation

0

1

1

1

Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs, Asynch. Data

Recirculation

1

0

0

X

Serial Mode; Synch. Serial Data Input, “A” Parallel Data Output

1

0

1

X

Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output

1

1

0

0

Parallel Mode; “B” Synch. Parallel Data Input, “A” Parallel Data Output

1

1

0

1

Parallel Mode; “B” Asynch. Parallel Data Input, “A” Parallel Data Output

1

1

1

0

Parallel Mode; “A” Synch, Parallel Data Input, “B” Parallel Data Output

1

1

1

1

Parallel Mode; “A” Asynch. Parallel Data Input, “B” Parallel Data Output

*Outputs change at positive transition of clock in the serial mode and when the A/S control input is “low” in the parallel mode. During

transfer from parallel to serial operation A/S should remain low in order to prevent DS transfer into Flip Flops.

1 = High Level

0 = Low Level

X = Don’t Care

CLS

CLS

p

n

CLS

CLS

p

n

CLM

CLM

p

n

CLM

CLM

p

n

P/S

P/S

p

n

K

K

p

n

L

L

p

n

Bn

VDD

VDD

VSS

VSS

Q’

M

Q’

M

N

Q’

N

1 OF 8 STAGES

SERIAL

DATA

D

VSS

VDD

VSS

PROTECTION NETWORK

ON ALL “A” AND “B”

DATA INPUTS

PROTECTION NETWORK

ON SERIAL DATA INPUT

An

Q (TO NEXT STAGE D)