KM416S1021C

REV. 1. May '98

CMOS SDRAM

Preliminary

The KM416S1021C is 16,777,216 bits synchronous high data

rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,

fabricated with SAMSUNG

′s high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the

use of system clock I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable burst

length and programmable latencies allow the same device to be

useful for a variety of high bandwidth, high performance mem-

ory system applications.

• JEDEC standard 3.3V power supply

• SSTL_3 (Class II) compatible with multiplexed address

• Dual banks operation

• MRS cycle with address key programs

- CAS latency (2 & 3)

- Burst length (1, 2, 4, 8 & Full page)

- Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (4K cycle)

GENERAL DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface

Samsung Electronics reserves the right to

change products or specification without

notice.

*

Bank Select

Data Input Register

512K x 16

512K x 16

Column Decoder

Latency & Burst Length

Programming Register

LCKE

LRAS

LCBR

LWE

LDQM

CLK

CKE

CS

RAS

CAS

WE

L(U)DQM

LWE

LDQM

DQi

CLK

ADD

LCAS

LWCBR

Timing Register

ORDERING INFORMATION

* KM416S1021CT-GS : CL=2 only

Part No.

Max Freq.

Interface Package

KM416S1021CT-G7

143MHz

SSTL_3

(Class II)

54

TSOP(II)

KM416S1021CT-GS

100MHz(CL=2)

KM416S1021CT-G8

125MHz