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GS71116AJ-7I Folha de dados(PDF) 7 Page - List of Unclassifed Manufacturers

Nome de Peças GS71116AJ-7I
Descrição Electrónicos  1Mb Asynchronous SRAM
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GS71116ATP/J/U
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.07 12/2004
7/16
© 2001, GSI Technology
AC Characteristics
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL
Read Cycle
Parameter
Symbol
-7
-8
-10
-12
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read cycle time
tRC
7—8—
10
12
ns
Address access time
tAA
—7—8—
10
12
ns
Chip enable access time (CE)tAC
—7—8—
10
12
ns
Byte enable access time (UB, LB)tAB
—3—
3.5
4
5
ns
Output enable to output valid (OE)tOE
—3—
3.5
4
5
ns
Output hold from address change
tOH
3—3—3
3
ns
Chip enable to output in low Z (CE)
tLZ*
3—3—3
3
ns
Output enable to output in low Z (OE)
tOLZ*
0—0—0
0
ns
Byte enable to output in low Z (UB, LB)
tBLZ*
0—0—0
0
ns
Chip disable to output in High Z (CE)
tHZ*
—3.5
4
5
6
ns
Output disable to output in High Z (OE)
tOHZ*
—3—
3.5
4
5
ns
Byte disable to output in High Z (UB, LB)
tBHZ*
3
3.5
3.5
3.5
tAA
tOH
tRC
Address
Data Out
Previous Data
Data valid


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