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FIN3384MTD Folha de dados(PDF) 3 Page - Fairchild Semiconductor |
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FIN3384MTD Folha de dados(HTML) 3 Page - Fairchild Semiconductor |
3 / 18 page 3 www.fairchildsemi.com TRANSMITTERS Pin Descriptions Connection Diagram FIN3383 and FIN3385 (28:4 Transmitter) Pin Assignment for TSSOP Truth Table H HIGH Logic Level L LOW Logic Level X Don’t Care Z High Impedance F Floating Note 1: The outputs of the transmitter or receiver will remain in a High Impedance state until VCC reaches 2V. Note 2: TxCLKOut r will settle at a free running frequency when the part is powered up, PwrDn is HIGH and the TxCLKIn is a steady logic level (L/H/Z). Pin Names I/O Type Number of Pins Description of Signals TxIn I 28/21 LVTTL Level Input TxCLKIn I 1 LVTTL Level Clock Input The rising edge is for data strobe. TxOut O 4/3 Positive LVDS Differential Data Output TxOut O 4/3 Negative LVDS Differential Data Output TxCLKOut O 1 Positive LVDS Differential Clock Output TxCLKOut O 1 Negative LVDS Differential Clock Output R_FB I 1 Rising Edge Clock (HIGH), Falling Edge Clock (LOW) PwrDn I 1 LVTTL Level Power-Down Input Assertion (LOW) puts the outputs in High Impedance state. PLL VCC I 1 Power Supply Pin for PLL PLL GND I 2 Ground Pins for PLL LVDS VCC I 1 Power Supply Pin for LVDS Output LVDS GND I 3 Ground Pins for LVDS Output VCC I 3 Power Supply Pins for LVTTL Input GND I 5 Ground pins for LVTTL Input NC No Connect Inputs Outputs TxIn TxCLKIn PwrDn (Note 1) TxOut r TxCLKOutr Active Active H L/H L/H Active L/H/Z H L/H X (Note 2) FActive H L L/H F F H L X (Note 2) XX L Z Z |
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