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AD9887AKS-140 Folha de dados(PDF) 11 Page - Analog Devices

Nome de Peças AD9887AKS-140
Descrição Electrónicos  Dual Interface for Flat Panel Displays
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Table II. Analog Interface Pin List
Pin
Pin
Pin
Type
Mnemonic
Function
Value
Number
Analog Video Inputs
RAIN
Analog Input for Converter R
0.0 V to 1.0 V
119
GAIN
Analog Input for Converter G
0.0 V to 1.0 V
110
BAIN
Analog Input for Converter B
0.0 V to 1.0 V
100
External
HSYNC
Horizontal SYNC Input
3.3 V CMOS
82
VSYNC
Vertical SYNC Input
3.3 V CMOS
81
Sync/Clock
SOGIN
Sync-on-Green Input
0.0 V to 1.0 V
108
Inputs
CLAMP
Clamp Input (External CLAMP Signal)
3.3 V CMOS
93
COAST
PLL COAST Signal Input
3.3 V CMOS
84
CKEXT
External Pixel Clock Input (to Bypass Internal PLL)
3.3 V CMOS
83
or 10 k
Ω to V
DD
CKINV
ADC Sampling Clock Invert
3.3 V CMOS
94
Sync Outputs
HSOUT
HSYNC Output (Phase-Aligned with DATACK and
DATACK)
3.3 V CMOS
139
VSOUT
VSYNC Output
3.3 V CMOS
138
SOGOUT
Composite Sync
3.3 V CMOS
140
Voltage Reference
REFOUT
Internal Reference Output (bypass with 0.1
µF to ground)
1.25 V
126
REFIN
Reference Input (1.25 V
± 10%)
1.25 V
± 10%
125
Clamp Voltages
RMIDSCV
Voltage output equal to the RED converter midscale voltage.
0.5 V
± 50%
120
RCLAMPVDuring midscale clamping, the RED Input is clamped to this pin.
0.0 V to 0.75 V
118
GMIDSCV
Voltage output equal to the GREEN converter midscale voltage.
0.5 V
± 50%
111
GCLAMPV
During midscale clamping, the GREEN Input is clamped to this pin.
0.0 V to 0.75 V
109
BMIDSCV
Voltage output equal to the BLUE converter midscale voltage.
0.5 V
± 50%
101
BCLAMPV
During midscale clamping, the BLUE Input is clamped to this pin.
0.0 V to 0.75 V
99
PLL Filter
FILT
Connection for External Filter Components for Internal PLL
78
Power Supply
VD
Main Power Supply
3.3 V
± 5%
PVD
PLL Power Supply (Nominally 3.3 V)
3.3 V
± 5%
VDD
Output Power Supply
3.3 V or 2.5 V
± 5%
GND
Ground
0 V
PIN FUNCTION DETAILS (ANALOG INTERFACE)
Inputs
RAIN
Analog Input for RED Channel
GAIN
Analog Input for GREEN Channel
BAIN
Analog Input for BLUE Channel
High-impedance inputs that accept the RED,
GREEN, and BLUE channel graphics signals,
respectively. For RGB, the three channels are
identical and can be used for any colors, but
colors are assigned for convenient reference.
For proper 4:2:2 formatting in a YUV appli-
cation, the Y channel must be connected to
the GAIN input, U must be connected to the
BAIN input, and V must be connected to the
RAIN input.
They accommodate input signals ranging
from 0.5 V to 1.0 V full scale. Signals should
be ac-coupled to these pins to support clamp
operation.
HSYNC
Horizontal Sync Input
This input receives a logic signal that estab-
lishes the horizontal timing reference and
provides the frequency reference for pixel
clock generation.
The logic sense of this pin is controlled by
serial register 0Fh Bit 7 (HSYNC Polarity).
Only the leading edge of HSYNC is active,
the trailing edge is ignored. When HSYNC
Polarity = 0, the falling edge of HSYNC is
used. When HSYNC Polarity = 1, the rising
edge is active.
The input includes a Schmitt trigger for noise
immunity, with a nominal input threshold
of 1.5 V.
Electrostatic Discharge (ESD) protection
diodes will conduct heavily if this pin is driven
more than 0.5 V above the maximum toler-
ance voltage (3.3 V), or more than 0.5 V
below ground.
VSYNC
Vertical Sync Input
This is the input for vertical sync.
SOGIN
Sync-on-Green Input
This input is provided to assist with processing
signals with embedded sync, typically on the
GREEN channel. The pin is connected to a
high-speed comparator with an internally
generated threshold, which is set to 0.15 V
above the negative peak of the input signal.
When connected to an ac-coupled graphics
signal with embedded sync, it will produce a
noninverting digital output on SOGOUT.
When not used, this input should be left
unconnected. For more details on this func-
tion and how it should be configured, refer to
the Sync-on-Green section.


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