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AD1835AAS Folha de dados(PDF) 11 Page - Analog Devices

Nome de Peças AD1835AAS
Descrição Electrónicos  2 ADC, 8 DAC, 96 kHz, 24-Bit Codecs
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
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AD1835AAS Folha de dados(HTML) 11 Page - Analog Devices

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REV. 0
AD1835A
–11–
(continued from page 1)
analog section. Each DAC has independent volume control
and clickless mute functions. The ADC comprises two 24-bit
conversion channels with multibit
-
modulators and deci-
mation filters.
The AD1835A also contains an on-chip reference with a
nominal value of 2.25 V.
The AD1835A contains a flexible serial interface that allows
for glueless connection to a variety of DSP chips, AES/EBU
receivers, and sample rate converters. The AD1835A can be
configured in left-justified, right-justified, I
2S, or DSP com-
patible serial modes. Control of the AD1835A is achieved by
means of an SPI compatible serial port. While the AD1835A
can be operated from a single 5 V supply, it also features a sepa-
rate supply pin for its digital interface that allows the device to
be interfaced to other devices using 3.3 V power supplies.
The AD1835A is available in a 52-lead MQFP package and is
specified for the industrial temperature range of –40ºC to +85ºC.
FUNCTIONAL OVERVIEW
ADCs
There are two ADC channels in the AD1835A, configured as
a stereo pair. Each ADC has fully differential inputs. The
ADC section can operate at a sample rate of up to 96 kHz.
The ADCs include on-board digital decimation filters with
120 dB stop-band attenuation and linear phase response,
operating at an oversampling ratio of 128 (for 48 kHz opera-
tion) or 64 (for 96 kHz operation).
ADC peak level information for each ADC may be read from
the ADC Peak 0 and ADC Peak 1 registers. The data is sup-
plied as a 6-bit word with a maximum range of 0 dB to –63 dB
and a resolution of 1 dB. The registers will hold peak informa-
tion until read; after reading, the registers are reset so that new
peak information can be acquired. Refer to the register descrip-
tion for details of the format. The two ADC channels have a
common serial bit clock and a left-right framing clock. The
clock signals are all synchronous with the sample rate.
The ADC digital pins, ABCLK and ALRCLK, can be set to
operate as inputs or outputs by connecting the
M/S pin to
ODVDD or DGND, respectively. When the pins are set as
outputs, the AD1835A will generate the timing signals. When
the pins are set as inputs, the timing must be generated by
the external audio controller.
DACs
The AD1835A has eight DAC channels arranged as four inde-
pendent stereo pairs, with eight fully differential analog outputs
for improved noise and distortion performance. Each channel
has its own independently programmable attenuator, adjustable
in 1024 linear steps. Digital inputs are supplied through four
serial data input pins (one for each stereo pair) and a common
frame (DLRCLK) and bit (DBLCK) clock. Alternatively, one
of the packed data modes can be used to access all eight chan-
nels on a single TDM data pin. A stereo replicate feature is
included where the DAC data sent to the first DAC pair is also
sent to the other DACs in the part. The AD1835A can accept
DAC data at a sample rate of 192 kHz on DAC 1 only. The
stereo replicate feature can then be used to copy the audio data
to the other DACs.
Each set of differential output pins sits at a dc level of VREF and
swings
1.4 V for a 0 dB digital input signal. A single op amp
third order external low-pass filter is recommended to remove
high frequency noise present on the output pins, as well as to
provide differential-to-single-ended conversion. Note that the use
of op amps with low slew rate or low bandwidth may cause high
frequency noise and tones to fold down into the audio band;
care should be exercised in selecting these components.
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases, this capacitor may be eliminated with little effect on
performance.
DAC and ADC Coding
The DAC and ADC output data stream is in a twos complement
encoded format. The word width can be selected from 16-bit,
20-bit, or 24-bit. The coding scheme is detailed in Table I.
Table I. Coding Scheme
Code
Level
01111......1111
+FS
00000......0000
0 (Ref Level)
10000......0000
–FS
Clock Signals
The DAC and ADC engines in the AD1835A are designed to
operate from a 24.576 MHz internal master clock (IMCLK). This
clock is used to generate 48 kHz and 96 kHz sampling on the
ADC and 48 kHz, 96 kHz, and 192 kHz on the DAC, although
the 192 kHz option is available only on one DAC pair. The stereo
replicate feature can be used to copy this DAC data to the other
DACs if required.
To facilitate the use of different MCLK values, the AD1835A
provides a clock scaling feature. The MCLK scaler can be
programmed via the SPI port to scale the MCLK by a factor
of 1 (pass-through), 2 (doubling), or 2/3. The default setting
of the MCLK scaler is 2, which will generate 48 kHz sam-
pling from a 12.288 MHz MCLK. Additional sample rates
can be achieved by changing the MCLK value. For example,
the CD standard sampling frequency of 44.1 kHz can be
achieved using an 11.2896 kHz MCLK. Figure 2 shows the
internal configuration of the clock scaler and converter engines.
To maintain the highest performance possible, the clock jitter of
the master clock signal should be limited to less than 300 ps rms,
measured using the edge-to-edge technique. Even at these levels,
extra noise or tones may appear in the DAC outputs if the jitter
spectrum contains large spectral peaks. It is highly recommended
that the master clock be generated by an independent crystal oscil-
lator. In addition, it is especially important that the clock signal not
be passed through an FPGA or other large digital chip before being
applied to the AD1835A. In most cases, this will induce clock jitter
due to the fact that the clock signal is sharing common power and
ground connections with unrelated digital output signals.


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