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74ALVCH16821DGG Folha de dados(PDF) 2 Page - NXP Semiconductors

Nome de Peças 74ALVCH16821DGG
Descrição Electrónicos  20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State
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Fabricante Electrônico  PHILIPS [NXP Semiconductors]
Página de início  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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Philips Semiconductors
Product specification
74ALVCH16821
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
2
1998 May 29
853-2066 19467
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
Current drive ± 24 mA at 3.0 V
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple V
CC and ground pins for minimum noise
and ground bounce
All data inputs have bus hold
Output drive capability 50Ω transmission lines @ 85°C
DESCRIPTION
The 74ALVCH16821 has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
When nOE is LOW, the data in the register appears at the outputs.
When nOE is HIGH, the outputs are in high impedance OFF state.
Operation of the nOE input does not affect the state of the flip-flops.
The 74ALVCH16821 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
nCP to nQn
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
2.6
2.5
ns
CI
Input capacitance
5.0
pF
C
Power dissipation capacitance per buffer
V = GND to VCC1
Outputs enabled
33
pF
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
Outputs disabled
17
pF
Fmax
Maximum clock frequency
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
250
350
MHz
NOTE:
1.
CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°C to +85°C
74ALVCH16821 DL
ACH16821 DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°C to +85°C
74ALVCH16821 DGG
ACH16821 DGG
SOT364-1


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