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STK12C68-IM
Note p: Once the software
STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
Note q: Noise on the E pin may trigger multiple read cycles from the same address and abort the address sequence.
Note r:
If the Chip Enable Pulse Width is less than tELQV (see READ CYCLE #2) but greater than or equal to tELEHN, then the data may not be valid at the end
of the low pulse, however the
STORE or RECALL will still be initiated.
Note s:
W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout.
Addresses #1 through #6 are found in the MODE SELECTION table. Address #6 determines whether the STK12C68-IM performs a
STORE or RECALL.
Note t:
E must be used to clock in the address sequence for the Software
STORE and RECALL cycles.
SOFTWARE STORE/RECALL CYCLE q,r,t
ADDRESS
E
DQ(Data Out)
VALID
ADDRESS #6
ADDRESS #1
VALID
HIGH IMPEDANCE
28
tAVAV
28
tAVAV
30
tAVELN
31
tELEHN
32
tEHAXN
23
tSTORE
22
tRECALL
29
tELQZ
ADDRESS #2
Std.
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
NO.
PARAMETER
UNITS
SYMBOLS
STK12C68-25-IM
STK12C68-35-IM
STK12C68-45-IM
27
tAVAV
tRC
Store/Recall Initiation Cycle Time
25
35
45
ns
28
tELQZ
p
Chip Enable to Output Inactive
650
650
650
ns
29
tAVELN
tAE
Address Set-up to Chip Enable
0
0
0
ns
30
tELEHN
p,q
tEP
Chip Enable Pulse Width
20
25
35
ns
31
tEHAXN
tEA
Chip Disable to Address Change
0
0
0
ns
32
tRESTORE
Power-up Recall Duration
550
550
550
µs
SOFTWARE STORE/RECALL CYCLE
(VCC = 5.0V ± 10%)d