Philips Semiconductors

Product specification

74F175A

Quad D flip-flop

1996 Mar 12

5

AC SETUP REQUIREMENTS FOR 74F175A

LIMITS

SYMBOL

PARAMETER

TEST

UNIT

CONDITION

MIN

TYP

MAX

MIN

MAX

MIN

MAX

Setup time, High or Low

Dn to CP

Waveform 2

3.0

3.0

3.5

3.5

4.0

4.0

ns

Hold time, High or Low

Dn to CP

Waveform 2

0.0

0.0

0.0

0.0

0.0

0.0

ns

CP Pulse width

High or Low

Waveform 1

3.0

4.0

3.5

5.0

4.0

5.5

ns

MR Pulse width

Low

Waveform 3

3.5

3.5

4.0

ns

Recovery time

MR to CP

Waveform 3

4.0

4.5

5.0

ns

AC WAVEFORMS

CP

SF00722

Waveform 1. Propagation delay for clock input to output, clock

pulse width, and maximum clock frequency

th(H)

ts(H)

CP

SF00191

VM

VM

VM

VM

VM

VM

th(L)

ts(L)

Dn

Waveform 2. Data setup time and hold times

CP

MR

SF00723

Waveform 3. Master Reset pulse width, Master Reset to output

delay and Master Reset to Clock recovery time