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74HCT7030 Folha de dados(PDF) 2 Page - NXP Semiconductors |
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74HCT7030 Folha de dados(HTML) 2 Page - NXP Semiconductors |
2 / 22 page December 1990 2 Philips Semiconductors Product specification 9-bit x 64-word FIFO register; 3-state 74HC/HCT7030 FEATURES • Synchronous or asynchronous operation • 3-state outputs • Master-reset input to clear control functions • 33 MHz (typ.) shift-in, shift-out rates with or without flags • Very low power consumption • Cascadable to 25 MHz (typ.) • Readily expandable in word and bit dimensions • Pinning arranged for easy board layout: input pins directly opposite output pins • Output capability: standard • ICC category: LSI GENERAL DESCRIPTION The 74HC/HCT7030 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no. 7A. The 74HC/HCT7030 is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 9 bits. A 33 MHz data-rate makes it ideal for high-speed applications. Even at high frequencies, the ICC dynamic is very low (fmax = 18 MHz; VCC = 5 V produces a dynamic ICC of 80 mA). If the device is not continuously operating at fmax, then ICC will decrease proportionally. With separate controls for shift-in (SI) and shift-out (SO), reading and writing operations are completely independent, allowing synchronous and asynchronous data transfers. Additional controls include a master-reset input (MR) and an output enable input (OE). Flags for data-in-ready (DIR) and data-out-ready (DOR) indicate the status of the device. Devices can be interconnected easily to expand word and bit dimensions. All output pins are directly opposite the corresponding input pins thus simplifying board layout in expanded applications. INPUTS AND OUTPUTS Data inputs (D0 to D8) As there is no weighting of the inputs, any input can be assigned as the MSB. The size of the FIFO memory can be reduced from the 9 × 64 configuration, i.e. 8 × 64, 7 × 64, down to 1 × 64, by tying unused data input pins to VCC or GND. Data outputs (Q0 to Q8) As there is no weighting of the outputs, any output can be assigned as the MSB. The size of the FIFO memory can be reduced from the 9 × 64 configuration as described for data inputs. In a reduced format, the unused data output pins must be left open circuit. Master-reset (MR) When MR is LOW, the control functions within the FIFO are cleared, and data content is declared invalid. The data-in-ready (DIR) flag is set HIGH and the data-out-ready (DOR) flag is set LOW. The output stage remains in the state of the last word that was shifted out, or in the random state existing at power-up. Status flag outputs (DIR, DOR) Indication of the status of the FIFO is given by two status flags, data-in-ready (DIR) and data-out-ready (DOR): Shift-in control (SI) Data is loaded into the input stage on a LOW-to-HIGH transition of SI. A HIGH-to-LOW transition triggers an automatic data transfer process (ripple through). If SI is held HIGH during reset, data will be loaded at the rising edge of the MR signal. Shift-out control (SO) A LOW-to-HIGH transition of SO causes the DOR flags to go LOW. A HIGH-to-LOW transition of SO causes upstream data to move into the output stage, and empty locations to move towards the input stage (bubble-up). Output enable (OE) The outputs Q0 to Q8 are enabled when OE = LOW. When OE = HIGH the outputs are in the high impedance OFF-state. DIR = HIGH indicates the input stage is empty and ready to accept valid data DIR = LOW indicates that the FIFO is full or that a previous shift-in operation is not complete (busy) DOR = HIGH assures valid data is present at the outputs Q0 to Q8 (does not indicate that new data is awaiting transfer into the output stage) DOR = LOW indicates the output stage is busy or there is no valid data |
Nº de peça semelhante - 74HCT7030 |
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Descrição semelhante - 74HCT7030 |
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