Philips Semiconductors

Product specification

74LV374

Octal D-type flip-flop; positive edge-trigger (3-State)

1997 Mar 20

7

AC WAVEFORMS

output load.

SV00343

CP INPUT

90%

10%

Figure 1. Waveforms showing the clock (CP) to output (Qn)

propagation delays, the clock pulse width, output transition

times and the maximum clock pulse frequency

outputs

disabled

SV00344

OE INPUT

GND

OUTPUT

LOW-to-OFF

OFF-to-LOW

OUTPUT

HIGH-to-OFF

OFF-to-HIGH

GND

outputs

enabled

outputs

enabled

Figure 2. Waveforms showing the 3-state enable and disable

times

t

su

t

su

SV00345

CP INPUT

GND

GND

NOTE: the shaded areas indicate when the input is permitted to change

for predictable output performance.

Figure 3.

Waveforms showing the data set-up and hold times

for the Dn input to the CP input

NOTE:

The shaded areas indicate when the input is permitted to change for

predictable output performance.