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74LVC10PWDH Folha de dados(PDF) 2 Page - NXP Semiconductors |
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74LVC10PWDH Folha de dados(HTML) 2 Page - NXP Semiconductors |
2 / 8 page Philips Semiconductors Product specification 74LVC10 Triple 3-input NAND gate 2 1997 Apr 28 853-1973 17997 FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Output capability: standard • I CC category: SSI DESCRIPTION The 74LVC10 is a high performance, low power, low voltage, Si gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC10 provides the 3-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf v2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay nA, nB, nC to nY CL = 50 pF; VCC = 3.3 V 3.9 ns CI Input capacitance 5.0 pF CPD Power dissipation capacitance per gate VI = GND to VCC1 26 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi ) (CL × VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 14-Pin Plastic SO –40 °C to +85°C 74LVC10 D 74LVC10 D SOT108-1 14-Pin Plastic SSOP Type II –40 °C to +85°C 74LVC10 DB 74LVC10 DB SOT337-1 14-Pin Plastic TSSOP Type I –40 °C to +85°C 74LVC10 PW 74LVC10PW DH SOT402-1 PIN CONFIGURATION SV00416 1 2 3 4 5 6 7 1A 1B 2A 2B 2C 2Y GND V CC 1C 1Y 3C 3B 3A 3Y 14 13 12 11 10 9 8 PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION 1, 3, 9 1A – 3A Data inputs 2, 4, 10 1B – 3B Data inputs 7 GND Ground (0 V) 12, 6, 8 1Y – 3Y Data outputs 13, 5, 11 1C – 3C Data inputs 14 VCC Positive supply voltage LOGIC SYMBOL 1C 1A 13 1 1B 2 2C 2A 5 3 2B 4 3C 3A 11 9 3B 10 SV00417 2Y 3Y 6 8 12 1Y |
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