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MC14534BCP Folha de dados(PDF) 6 Page - Motorola, Inc |
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MC14534BCP Folha de dados(HTML) 6 Page - Motorola, Inc |
6 / 9 page MOTOROLA CMOS LOGIC DATA MC14534B 6 SCANNER TIMING DIAGRAM NOTE: If Mode B = 1, the first decade is inhibited and S1 will not go high, and the cycle will be shortened to four stages. DS5 is selected automatically when Scanner Reset goes high. TEN THOUSANDS THOUSANDS HUNDREDS TENS UNITS SCANNER CLOCK SCANNER RESET DS1 DS2 DS3 DS4 DS5 ERROR DETECTION TIMING DIAGRAM NOTE: Error detector looks for inverted pulse on Clock B. Whenever a positive edge at Clock A is not accompanied by a negative pulse at Clock B (or vice–versa) within a time period of the one–shots an error is counted. Three errors result in Error Out to go to a “1”. If error detection is not needed, tie Clock B high or low and leave Pins 1 and 22 unconnected. CLOCK A CLOCK B RESET ERROR OUT GOOD PULSE ERROR 1 ERROR 2 ERROR 3 ERROR 4 GOOD PULSE CLOCK SKEW RANGE NOTES: 1. The skew is the time difference between the low–to–high transition of CA to the high–to– low transition of CB or vice–versa. Capacitors C1 = C22 tied from pins 1 and 22 to VSS. 2. This graph is accurate for C1 = C22 ≥ 100 pF. 3. When the error detection circuitry in not used, pins 1 and 22 are left open. 1000 500 300 100 50 30 10 5.0 3.0 1.0 3.0 5.0 7.0 9.0 11 13 15 17 VDD (Vdc) SKEW IN THIS RANGE RESULTS IN COUNTED ERROR. MAX SKEW IN THIS RANGE RESULTS IN NO ERROR COUNTED. TYP MIN SKEW IN THIS RANGE MAY OR MAY NOT RESULT IN COUNTED ERROR. |
Nº de peça semelhante - MC14534BCP |
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Descrição semelhante - MC14534BCP |
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