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document is about a product in its fully tested and characterized phase. All fea-

tures described herein are supported. Contact AMCC for updates to this docu-

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Empowering Intelligent Optical Networks

Product Brief

HUDSON 2.0

Variable Rate Digital Wrapper Framer/Deframer, PM, and FEC Device

Part Number S19203CBI20, Revision 1.3, May 2003

• Core logic runs on a 1.8 V power supply to reduce power con-

sumption and LVCMOS I/O are 3.3 V compatible.

• Two independent 16-bit parallel LVDS input and output ports at

up to 693.483 MHz (11.096 Gbps).

• Datapath options: Configurable as two completely independent

data stream for full duplex operation. Configurable as a single

data stream for regenerator operation with dual redundant I/O for

optional protection switching. Either input port can be directly

connected to either output port for loopback testing or bypass

operation.

• Supports SONET OC-192 Performance Monitoring at the input of

the encoder side and at the output of the decoder side.

• Supports G.709 “Interfaces for the optical transport network

(OTN)” standard including specified frame structure, all overhead

monitoring and processing, Maintenance signals, synchronous

and asynchronous mapping and demapping.

• ON/OFF control of Reed-Solomon (255,239) FEC Encoding/

Decoding and error correction.

• Support for System test and diagnostics: internal BER generator,

PRBS pattern generator and pattern analyzer for bit error rate

testing capability.

• Four programmable integer clock dividers to simplify clock gener-

ation.

• Support for signal aggregation to higher rates via chip synchroni-

zation feature.

• General Purpose Processor Interface: Gluess interface to

MPC860, 25 MHz to 50 MHz bus speed. Also compatible with

Intel microprocessor bus via Busmode selector.

• Low power: 0.18 micron CMOS technology.

Applications

• 10 Gigabit Digital Wrapper Performance Monitor and Framer

• Protocol Independent DWDM Metropolitan Area Networks

• Optical Cross-connects

• OC-192 Port interface

• Fiber optic terminators, repeaters, and test equipment

The Hudson is a fully integrated, Variable Rate Digital Wrapper Framer/Deframer, Performance Monitor, and Forward Error Correction (FEC)

device supporting the Digital Wrapper transmission standards for OTU1, OTU2, ODU1, ODU2, OPU1, and OPU2 as specified in G.709. The

Hudson implements Performance Monitoring and overhead processing functions on the Digital Wrapper overhead bytes. In addition, the

device contains SONET/SDH Performance Monitoring to verify the validity of the SONET/SDH OC-192 client data. The device can operate

from a low rate of 6.25 MHz to a high rate of 693.483 MHz. Data entering and leaving the chip can be optionally deframed and framed,

descrambled and scrambled, and decoded and encoded with forward error correction information.

Figure 1: Block Diagram

D E C O D E IN [15:0]

DUP L E X O UT[1 5 :0 ]

DE C O H

Mo n /D r o p

FE C

D ec oder

DE C

1:8

De mu x

DUP O

UT 1 :8

Mu x

DE C

SON E T

PM

D e c ode (D E C ) S ide

D U PT XC LK_O U T

DE CR X C LK

Ra te

Ma tch

FIFO

Pattern

Analy z e r

EN C

8:1

Mu x

EN C O H

Fra m e

G en &

FE C

Enc oder

EN C D A T AO U T [1 5:0]

EN C O H

Add

TX _ O H _ CL K

IN S F P

IN SSF P

TX _ O H _ DA TA [7 :0]

TX _ O H _ IN S

DU P IN

1:8

De mu x

DUP L E X IN[1 5:0 ]

E n c ode (E N C ) S ide

EN C T XC LK

D U PR XC LK

Ra te

Ma tc h

FIFO

Pa tte rn

G ener ator

DUP O H

F ram er

DE C O H

F r am er

OC H

D e scra m

& S C /O H

Mo n/D r o p

DE C O H

In s &

Sc ra m b le r

DE C_ IN S C L K

DE C _ IN S _ F P

D E C _ IN S_SF P

D E CINS [7 :0 ]

DE C_ IN S _ E N

H u d s on 2.0

RX _ O H_ C L K

RX _ O H_ D A TA [7 :0 ]

DRO P F P

DR O P S F P

E N C_DR P C L K

E N C _ DRP [7 :0 ]

E N C _ DRP _ F P

EN C _ D R P_SF P

Clo c k

D iv ider

D E C R XC LK _D IV

Clo c k

D iv ider

D U PR X C LK_D IV

Clo c k

Div id e r

EN C T XC LK _D IV

Clo c k

Div id e r

D U PT XC LK _D IV

EN C

SO N E T

PM

Sy nc

B u ffe r

IN PUT_PORT _S W A P

IN PUT_PO RT_S W A P

D EC _IN _S E L[1 :0]

PA T _GEN_ ON

DU P_ OUT _SEL[1:0]

OU T P U T _ POR T _ S W AP

EN C_IN _SEL

E N C _O U T _ SE L [1:0]

O U TPU T _P O R T_SW AP

0

1

1

0

00

10

01

01

01, 11

00

11

00

10

10

00, 01

10

00

01

0

0

1

1

0

0

1

1

00,10