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AD5532B Folha de dados(PDF) 11 Page - Analog Devices |
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AD5532B Folha de dados(HTML) 11 Page - Analog Devices |
11 / 16 page REV. A AD5532B –11– FUNCTIONAL DESCRIPTION The AD5532B can be thought of as consisting of 32 DACs and an ADC (for ISHA mode) in a single package. In DAC mode, a 14-bit digital word is loaded into one of the 32 DAC registers via the serial interface. This is then converted (with gain and offset) into an analog output voltage (VOUT0–VOUT31). To update a DAC’s output voltage, the required DAC is addressed via the serial port. When the DAC address and code have been loaded, the selected DAC converts the code. On power-on, all the DACs, including the offset channel, are loaded with zeros. Each of the 33 DACs is offset internally by 50 mV (typ) from GND so the outputs VOUT0 to VOUT31 are 50 mV (typ) on power-on if the OFFS_IN pin is driven directly by the on-board offset channel (OFFS_OUT), i.e., if OFFS_IN = OFFS_OUT = 50 mV = > VOUT = (Gain × VDAC) – (Gain –1) × VOFFS_IN = 50 mV. Output Buffer Stage—Gain and Offset The function of the output buffer stage is to translate the 50 mV–3 V typical output of the DAC to a wider range. This is done by gaining up the DAC output by 3.52 and offsetting the voltage by the voltage on OFFS_IN pin. VV V OUT DAC OFFS IN =× × 352 252 .– . _ VDAC is the output of the DAC. VOFFS_IN is the voltage at the OFFS_IN pin. Table I shows how the output range on VOUT relates to the offset voltage supplied by the user: Table I. Sample Output Voltage Ranges VOFFS_IN VDAC (Typ) VOUT (Typ) (V) (V) (V) 0 0.05 to 3 0.176 to 10.56 1 0.05 to 3 –2.34 to +8.04 2.130 0.05 to 3 –5.192 to +5.192 VOUT is limited only by the headroom of the output amplifiers. VOUT must be within maximum ratings. Offset Voltage Channel The offset voltage can be externally supplied by the user at OFFS_IN or it can be supplied by an additional offset voltage channel on the device itself. The offset can be set up in two ways. In ISHA mode the required offset voltage is set up on VIN and acquired by the offset channel. In DAC mode, the code corresponding to the offset value is loaded directly into the offset DAC. This offset channel’s DAC output is directly connected to the OFFS_OUT pin. By connecting OFFS_OUT to OFFS_IN this offset voltage can be used as the offset voltage for the 32 output amplifiers. The offset must be chosen so that VOUT is within maximum ratings. Reset Function The reset function on the AD5532B can be used to reset all nodes on this device to their power-on-reset condition. This is imple- mented by applying a low going pulse of between 90 ns and 200 ns to the TRACK/RESET pin on the device. If the applied pulse is less than 90 ns, it is assumed to be a glitch and no operation takes place. If the applied pulse is wider than 200 ns, this pin adopts its track function on the selected channel, VIN is switched to the output buffer, and an acquisition on the channel will not occur until a rising edge of TRACK. ISHA Mode In ISHA mode the input voltage VIN is sampled and converted into a digital word. The noninverting input to the output buffer (gain and offset stage) is tied to VIN during the acquisition period to avoid spurious outputs while the DAC acquires the correct code. This is completed in 16 µs max. At this time, the updated DAC output assumes control of the output voltage. The output voltage of the DAC is connected to the noninverting input of the output buffer. Since the channel output voltage is effectively the output of a DAC, there is no droop associated with it. As long as power is maintained to the device, the output voltage will remain constant until this channel is addressed again. Since the internal DACs are offset by 70 mV (max) from GND, the minimum VIN in ISHA mode is 70 mV. The maximum VIN is 2.96 V due to the upper dead band of 40 mV (max). Analog Input (ISHA Mode) The equivalent analog input circuit is shown in Figure 8. The capacitor C1 is typically 20 pF and can be attributed to pin capacitance and 32 off-channels. When a channel is selected, an extra 7.5 pF (typ) is switched in. This capacitor C2 is charged to the previously acquired voltage on that particular channel so it must charge/discharge to the new level. It is essential that the external source can charge/discharge this additional capacitance within 1 µs to 2 µs of channel selection so that V IN can be acquired accurately. For this reason a low impedance source is recommended. VIN C1 20pF C2 7.5pF ADDRESSED CHANNEL Figure 8. Analog Input Circuit Large source impedances will significantly affect the performance of the ADC. This may necessitate the use of an input buffer amplifier. TRACK Function (ISHA Mode) Normally in ISHA mode of operation, TRACK is held high and the channel begins to acquire when it is addressed. However, if TRACK is low when the channel is addressed, V IN is switched to the output buffer and an acquisition on the channel will not occur until a rising edge of TRACK. At this stage the BUSY pin will go low until the acquisition is complete, at which point the DAC assumes control of the voltage to the output buffer and VIN is free to change again without affecting this output value. This is useful in an application where the user wants to ramp up VIN until VOUT reaches a particular level (Figure 9). VIN does not need to be acquired continuously while it is ramping up. TRACK can be kept low and only when V OUT has reached its desired voltage is TRACK brought high. At this stage, the acquisition of VIN begins. In the example shown, a desired voltage is required on the output of the pin driver. This voltage is represented by one input to a comparator. The microcontroller/microprocessor ramps up the input voltage on VIN through a DAC. TRACK is kept low while the voltage on VIN ramps up so that VIN is not continu- ally acquired. When the desired voltage is reached on the output |
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