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STP04CM596MTR Folha de dados(PDF) 11 Page - STMicroelectronics |
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STP04CM596MTR Folha de dados(HTML) 11 Page - STMicroelectronics |
11 / 24 page STP04CM596 Timing diagrams 11/24 6 Timing diagrams Figure 7. Timing diagram Note: The latches circuit holds data when the LE terminal is Low. 1 When the LE terminal is at a High level, the latch circuit holds the data it passes from the input to the output. 2 When the OE terminal is at a Low level, the output terminals OUT0 to OUT3 respond to the data, either ON or OFF. 3 When the OE terminal is at a High level, it switches off all the data on the output terminal. |
Nº de peça semelhante - STP04CM596MTR |
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Descrição semelhante - STP04CM596MTR |
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