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AD1938XSTZ Folha de dados(PDF) 10 Page - Analog Devices |
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AD1938XSTZ Folha de dados(HTML) 10 Page - Analog Devices |
10 / 30 page AD1935/AD1936/AD1937/AD1938/AD1939 Preliminary Technical Data Rev. Pr I | Page 10 of 30 oscillator generate the master clock. In addition, it is especially important that the clock signal should not be passed through an FPGA, CPLD, or other large digital chip (such as a DSP) before being applied to the AD193X. In most cases, this will induce clock jitter due to the sharing of common power and ground connections with other unrelated digital output signals. When the PLL is used, jitter in the reference clock will be attenuated above a certain frequency depending on the loop filter. Reset and Power-Down Reset will set all the control registers to their default settings. To avoid pops, reset does not power down the analog outputs. After reset is de-asserted, an initialization routine will run inside the AD193X. This initialization lasts for approximately XX MCLKs. The power-down bits in the PLL and Clock Control 0, DAC Control 1, and ADC Control 1 registers will power down the respective sections. All other register settings are retained. Serial Control Port The AD193X has an SPI or I2C compatible control port that permits programming and reading back the internal control registers for the ADCs, DACs, and clock system. There is also a stand-alone mode available for operation without serial control, configured at reset using the serial control pins. All registers are set to default except Internal MCLK Enable is set to 1 and ADC BCLK and LRCLK Master/Slave is set by COUT/SDA. Refer to Table 10 for details. ADC Clocks: CIN/ADR0 COUT/SDA CCLK/SCL CLATCH/ADR1 Slave 0 0 0 0 Master 0 1 0 0 Table 11. Stand-alone Mode Selection The SPI control port of the AD1938 and AD1939 is a 4-wire serial control port. The format is similar to the Motorola SPI format except the input data-word is 24 bits wide. The serial bit clock and latch may be completely asynchronous to the sample rate of the ADCs and DACs. Figure 10 shows the format of the SPI signal. The first byte is a global address with a read/write bit. For the AD193X the address is 0x04, shifted left 1 bit due to the R/W bit. The second byte is the AD193X register address and the third byte is the data. CLATCH CCLK CIN COUT D0 D8 D0 D15 D14 D9 D8 tCCH tCCL D9 tCDS tCDH tCLS tCLH tCOD tCOTS tCCP tCOE Figure 10. Format of SPI Signal The I2C interface of the AD1936 and AD1937 is a two wire interface consisting of a clock line, SCL and a data line, SDA. SDA is bidirectional and the AD1936 and AD1937 will drive SDA either to acknowledge the master, ACK, or to send data during a read operation. The SDA pin for the I2C port is an open drain collector and requires a 1KΩ pullup resistor. A write or read access occurs when the SDA line is pulled low while the SCL line is high indicated by START in the timing diagrams. SDA is only allowed to change when SCL is low except when a START or STOP condition occurs as shown in figures 3 and 4. The first eight bits of the access consist of the device address and the R/W bit. The device address consists of an internal built-in address (0x04) and two address pins, AD1 and AD0. The two address pins allow up to four AD1936s and AD1937s to be used in a system. Initiating a write operation to the AD1936 and AD1937 involves sending a START condition and then sending the device address with the R/W set low. The AD1936 and AD1937 will respond by issuing an ACK to indicate that it has been addressed. The user then sends a second frame telling the AD1936 and AD1937 which register is required to be written to. Another ACK is issued by the AD1936 and AD1937. Finally the user can send another frame with the 8 data bits required to be written to the register. A third ACK is issued by the AD1936 and AD1937 after which the user can send a STOP condition to complete the data transfer. A read operation requires that the user first write to the AD1936 and AD1937 to point to the correct register and then read the data. This is achieved by sending a START condition followed by the device address frame, with R/W low, and then the register address frame. Following the ACK from the AD1936 and AD1937 the user must issue a REPEATED START condition. This is identical to a START condition. The next frame is the device address with R/W set high. On the next frame the AD1936 and AD1937 will output the register data on the SDA line. A STOP condition completes the read operation. Figure 3 and Figure 4 show examples of writing to and reading from the DAC 1 Left Volume Register (address = 0x06) |
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