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STD90N02L-1 Folha de dados(PDF) 9 Page - STMicroelectronics |
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9 / 17 page STD90N02L - STD90N02L-1 9/17 Appendix A The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the wotking temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. The low side (SW2) device requires: Very low RDS(on) to reduce conduction losses Small Qgls to reduce the gate charge losses Small Coss to reduce losses due to output capacitance Small Qrr to reduce losses on SW1 during its turn-on The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon. The high side (SW1) device requires: Small Rg and Lg to allow higher gate current peak and to limit the voltage feedback on the gate Small Qg to have a faster commutation and to reduce gate charge losses Low RDS(on) to reduce the conduction losses Figure 14. Synchronous buck converter |
Nº de peça semelhante - STD90N02L-1 |
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Descrição semelhante - STD90N02L-1 |
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