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TPA3101D2PHP Folha de dados(PDF) 6 Page - Texas Instruments |
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TPA3101D2PHP Folha de dados(HTML) 6 Page - Texas Instruments |
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6 / 38 page  www.ti.com TPA3101D2 SLOS473A – DECEMBER 2005 – REVISED FEBRUARY 2006 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION QFN HTQFP NAME NO. NO. ROUTP 41, 42 41, 42 O Class-D 1/2-H-bridge positive output for right channel. PVCCR 34, 35 34, 35 Power supply for right channel H-bridge, not connected to PVCCL or AVCC. BSRP 43 43 I/O Bootstrap I/O for right channel, positive high-side FET. AGND 4, 17 4, 17 Analog ground for digital/analog cells in core. ROSC 14 14 I/O I/O for current setting resistor of ramp generator. Master/Slave select for determining direction of SYNC terminal. HIGH=Master mode, SYNC terminal is an output; LOW = slave mode, MSTR/SLV 10 10 I SYNC terminal accepts a clock input. TTL logic levels with compliance to VREG. Clock input/output for synchronizing multiple class-D devices. Direction SYNC 11 11 I/O determined by MSTR/SLV terminal. Input signal not to exceed VREG. Reference for preamplifier. Nominally equal to 1.25 V. Also controls start-up VBYP 16 16 O time via external capacitor sizing. 4-V regulated output for use by internal cells, GAINx, MUTE, and VREG 15 15 O MSTR/SLV pins only. Not specified for driving other external circuitry. High-voltage analog power supply. Not internally connected to PVCCR or AVCC 48 47, 48 PVCCL. 1, 7, 12, NC 13, 24, 25, Not internally connected. 36, 37, 47 Connect to AGND and PGND – should be star point for both grounds. Internal resistive connection to AGND and PGND. Thermal vias on the PCB Thermal Pad - - - should connect this pad to a large copper area on an internal or bottom layer for the best thermal performance. The Thermal Pad must be soldered to the PCB for mechanical reliability. 6 Submit Documentation Feedback |
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