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MC10E197FNR2 Folha de dados(PDF) 11 Page - ON Semiconductor

Nome de Peças MC10E197FNR2
Descrição Electrónicos  5V ECL Data Separator
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Fabricante Electrônico  ONSEMI [ON Semiconductor]
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11
Voltage Divider Subsection
The element values for the voltage divider network are
calculated using the relationships presented in Equations 8,
9, and 10 with the constraint that this divider network must
produce a voltage that lies within the range 1.3 V + VEE to
2.6 V + VEE.
Restating Equation 9,
Kd =
Kol
Kφ * Ko * K1 * Kl
From the root locus analysis Kol is determined to be:
Kol = 1.585 e51
V
mA sec3
From Equation 3
K1 = A1 *
1
CIN
and the gain constant K1 is:
K1 = 8.90 e21
V
mA sec
From Equation 5
Kl = Al *
RA
RlA
and the gain constant Kl is:
Kl = 2.48 e15
V
V
Having determined the gain constant Kd , the value of Rv, is
selected such that the constraints Rv > Ro and:
Kd
2π⎥ p2
=
Ro
Ro + Rv
are fulfilled. The pole position P2 is determined from the
root locus analysis to be:
P2 = − 3.06MHz
Hence, Rv is selected to be:
Rv = 2.15kΩ
and Ro is calculated to be:
Ro = 700Ω
Finally, using Equation 8a:
Cd =
1
Rv Kd
eqt. 8a
the capacitor value, Cd is:
Cd = 98pF
Note that the voltage divider section can be used to set the
gain, but the designer is cautioned to be sure the input value
to VCOIN is within the correct range.
Component Scaling
As mentioned, these design equations were developed for
a data rate of 23 Mbit/sec. If the data rate is different from
the nominal design value the reactive elements must be
scaled accordingly. The following equations are provided to
facilitate scaling and were derived with the assumptions that
a 2:7 coding scheme is used and that the RDCLK signal is
twice the frequency of the data clock.
CIN = 278 *
46
f
eqt. 11
(pF)
46
f
Cd = 98 *
eqt. 12
(pF)
where f is the RDCLK frequency in MHz.
Example for an 11 Mbit/sec Data Rate
As an example of scaling, assume the given filter and a 2:7
code are used but the data rate is 11 Mbit/sec. The dynamic
pole positions, and therefore the bandwidth of the loop filter,
are a function of the data rate. Thus a slower data rate will
force the dynamic poles and the bandwidth to move to a
lower frequency. From Equation 11 the value of CIN is:
CIN = 581pF
and from Equation 12 the value of Cd is:
Cd = 205pF
Thus the element values for the filter are:
Filter Input Subsection:
CIN = 581pF
R1 = 1kΩ
Integrator Subsection:
CA = 0.1μF
RA = 5.11kΩ
RlA = 5.11kΩ
Voltage Divider Subsection:
Cd = 205pF
Rv = 2.15kΩ
Ro = 700kΩ
Note, the poles P1 and P2 are now located at:
P1 = − 274kHz
P2 = −1.47MHz


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