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MC100EP56DR2G Folha de dados(PDF) 7 Page - ON Semiconductor

Nome de Peças MC100EP56DR2G
Descrição Electrónicos  3.3V / 5V ECL Dual Differential 2:1 Multiplexer
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Fabricante Electrônico  ONSEMI [ON Semiconductor]
Página de início  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC100EP56DR2G Folha de dados(HTML) 7 Page - ON Semiconductor

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MC10EP56, MC100EP56
http://onsemi.com
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Table 9. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)
−40°C
25°C
85°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fmax
Maximum Frequency
(See Figure 2 Fmax/JITTER)
> 3
> 3
> 3
GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
D to Q, Q
SEL to Q, Q
COM_SEL to Q, Q
250
250
250
340
340
350
450
450
450
270
270
270
360
340
360
470
470
470
300
300
300
400
400
400
500
500
500
ps
tSKEW
Within−Device Skew (Note 21)
Device to Device Skew
50
100
200
50
100
200
50
100
200
ps
tJITTER
Random Clock Jitter
(See Figure 2 Fmax/JITTER)
0.2
< 1
0.2
< 1
0.2
< 1
ps
VPP
Input Voltage Swing
(Differential Configuration)
150
800
1200
150
800
1200
150
800
1200
mV
tr
tf
Output Rise/Fall Times
Q, Q
(20% − 80%)
70
120
170
80
130
180
100
150
230
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
21.Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
Figure 2. Fmax/Jitter @ 255C
FREQUENCY (GHz)
1
2
3
4
5
6
7
8
(JITTER)
9
3.3 V
10
800
1000
600
400
200
1.0
1.5
2.0
2.5
3.0
0
5 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q
D
Zo = 50 W
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V


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