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MC74VHCT50AMELG Folha de dados(PDF) 2 Page - ON Semiconductor

Nome de Peças MC74VHCT50AMELG
Descrição Electrónicos  Noninverting Buffer / CMOS Logic Level Shifter with LSTTL?묬ompatible Inputs
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Fabricante Electrônico  ONSEMI [ON Semiconductor]
Página de início  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC74VHCT50AMELG Folha de dados(HTML) 2 Page - ON Semiconductor

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MC74VHCT50A
http://onsemi.com
2
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
*0.5 to )7.0
V
VIN
DC Input Voltage
*0.5 v VI v )7.0
V
VOUT
DC Output Voltage
Output in HIGH or LOW State (Note 1)
*0.5 v VO v )7.0
V
IIK
DC Input Diode Current
*20
mA
IOK
DC Output Diode Current
$20
mA
IO
DC Output Source/Sink Current
$25
mA
ICC
DC Supply Current per Supply Pin
$50
mA
IGND
DC Ground Current per Ground Pin
$50
mA
TSTG
Storage Temperature Range
*65 to )150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
_C
TJ
Junction Temperature under Bias
)150
_C
qJA
Thermal Resistance
SOIC
TSSOP
125
170
_C/W
PD
Power Dissipation in Still Air
SOIC
TSSOP
500
450
mW
VESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 2000
> 200
2000
V
ILatch−Up
Latch−Up Performance
Above VCC and Below GND at 85_C (Note 5)
$300
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Max
Unit
DC Supply Voltage
VCC
2.0
5.5
V
DC Input Voltage
VIN
0.0
5.5
V
DC Output Voltage
VCC = 0
High or Low State
VOUT
0.0
0.0
5.5
VCC
V
Operating Temperature Range
TA
−55
+125
°C
Input Rise and Fall Time
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
tr , tf
0
0
100
20
ns/V
3.0V
GND
50%
50% VCC
A
Y
tPHL
tPLH
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 1. Switching Waveforms
Figure 2. Test Circuit
VOH
VOL


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