MC100LVEL59

http://onsemi.com

2

D1a

Figure 1. Logic Diagram and Pinout: 20−Lead SOIC (Top View)

SEL0

SEL1 D2a

17

18

16

15

14

13

12

4

3

5678

9

Q0

11

10

Q1

Q1

Q2

Q2

D0a

19

20

2

1

Q0

D0b

D1b

COM_SEL

D2b SEL2

10

10

10

to Power Supply to guarantee proper operation.

Table 1. PIN DESCRIPTION

Function

ECL Input Data a

ECL Input Data b

ECL Individual Select Input

ECL Common Select Input

ECL Differential Outputs

Positive Supply

Negative Supply

Pins

D0a−D2a

D0b−D2b

SEL0−SEL2

COM_SEL

Q0−Q2; Q0−Q2

SEL

H

L

Table 2. TRUTH TABLE

Data

a

b

Table 3. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

PECL Mode Power Supply

8 to 0

V

NECL Mode Power Supply

−8 to 0

V

PECL Mode Input Voltage

NECL Mode Input Voltage

6 to 0

−6 to 0

V

V

Output Current

Continuous

Surge

50

100

mA

mA

Operating Temperature Range

−40 to +85

°C

Storage Temperature Range

−65 to +150

°C

Thermal Resistance (Junction to Ambient)

0 lfpm

500 lfpm

20 SOIC

20 SOIC

140

100

°C/W

°C/W

Thermal Resistance (Junction to Case)

Standard Board

20 SOIC

30 to 35

°C/W

Wave Solder

<2 to 3 sec @ 248°C

265

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.