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CAT34RC02 Folha de dados(PDF) 5 Page - Catalyst Semiconductor |
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CAT34RC02 Folha de dados(HTML) 5 Page - Catalyst Semiconductor |
5 / 14 page Discontinued Part CAT34RC02 5 Doc No. 1052, Rev. O © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice I2C BUS PROTOCOL The I2C bus consists of two ‘wires’, SCL and SDA. The two ‘wires’ are connected to the supply (VCC) via pull-up resistors. Master and Slave devices connect to the bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. (1) Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). (2) During a data transfer, the data line must remain stable whenever the SCL line is high. An SDA transition while SCL is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START condition acts as a ‘wake-up’ call for the Slave devices. A Slave will not respond to commands unless the MASTER generates a START condition. STOP Condition The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP condition starts the internal write cycle, when following a WRITE command and sends the Slave into standby mode, when following a READ command. Device Addressing The Master initiates a data transfer by creating a START condition on the bus. The Master then broadcasts an 8- bit serial Slave address. The four most significant bits of the Slave address (the ‘preamble’) are fixed to 1010 (Ah), for normal read/write operations and 0110 (6h) for Software Write Protect (SWP) operations (Fig. 5). The next three bits, A2, A1 and A0, select one of eight possible Slave devices. The last bit, R/ W, specifies whether a Read (1) or Write (0) operation is to be performed. Acknowledge After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle. The Slave will aslo acknowledge the 8-bit byte address and every data byte presented in WRITE mode. In READ mode the Slave shifts out eight bits of data, and then ‘releases’ the SDA line durng the 9th clock cycle. If the Master acknowledges in the 9th clock cycle (by pulling down the SDA line), then the Slave continues transmitting. When data transfer is complete, the Master responds with a NoACK (it does not acknowledge the last data byte) and the Slave stops transmitting and waits for a STOP condition. Figure 4. Acknowledge Timing Figure 5. Slave Address Bits ACKNOWLEDGE 1 START SCL FROM MASTER 89 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER 1 DEVICE ADDRESS 010 A2 A1 A0 R/W 0 110 A2 A1 A0 R/W Normal Read and Write Programming the Write Protect Register |
Nº de peça semelhante - CAT34RC02_05 |
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Descrição semelhante - CAT34RC02_05 |
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