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MC14556BF Folha de dados(PDF) 1 Page - ON Semiconductor |
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MC14556BF Folha de dados(HTML) 1 Page - ON Semiconductor |
1 / 6 page © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 8 1 Publication Order Number: MC14555B/D MC14555B, MC14556B Dual Binary to 1−of−4 Decoder/Demultiplexer The MC14555B and MC14556B are constructed with complementary MOS (CMOS) enhancement mode devices. Each Decoder/Demultiplexer has two select inputs (A and B), an active low Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2, Q3). The MC14555B has the selected output go to the “high” state, and the MC14556B has the selected output go to the “low” state. Expanded decoding such as binary−to−hexadecimal (1−of−16), etc., can be achieved by using other MC14555B or MC14556B devices. Applications include code conversion, address decoding, memory selection control, and demultiplexing (using the Enable input as a data input) in digital data transmission systems. Features • Diode Protection on All Inputs • Active High or Active Low Outputs • Expandable • Supply Voltage Range = 3.0 Vdc to 18 Vdc • All Outputs Buffered • Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load Over the Rated Temperature Range • Pb−Free Packages are Available* MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter Symbol Value Unit DC Supply Voltage Range VDD − 0.5 to +18.0 V Input or Output Voltage Range (DC or Transient) Vin, Vout − 0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin Iin, Iout ±10 mA Power Dissipation, per Package (Note 1) PD 500 mW Ambient Temperature Range TA − 55 to +125 °C Storage Temperature Range Tstg − 65 to +150 °C Lead Temperature (8−Second Soldering) TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ °C From 65°C To 125°C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ORDERING INFORMATION x = 5 or 6 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb−Free Package MARKING DIAGRAMS PDIP−16 P SUFFIX CASE 648 SOIC−16 D SUFFIX CASE 751B 1 16 1455xBG AWLYWW SOEIAJ−16 F SUFFIX CASE 966 1 16 MC1455xB ALYWG 16 1 MC1455xBCP AWLYYWWG 1 1 1 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 Q0B BB AB EB VDD Q3B Q2B Q1B Q0A BA AA EA VSS Q3A Q2A Q1A MC14555B 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 Q0B BB AB EB VDD Q3B Q2B Q1B Q0A BA AA EA VSS Q3A Q2A Q1A MC14556B PIN ASSIGNMENTS |
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