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ATMEGA8535-16AC Folha de dados(PDF) 69 Page - ATMEL Corporation |
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ATMEGA8535-16AC Folha de dados(HTML) 69 Page - ATMEL Corporation |
69 / 321 page 69 ATmega8535(L) 2502K–AVR–10/06 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 36. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. MCU Control and Status Register – MCUCSR • Bit 6 – ISC2: Interrupt Sense Control 2 The asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG I-bit and the corresponding interrupt mask in GICR are set. If ISC2 is written to zero, a falling edge on INT2 activates the interrupt. If ISC2 is written to one, a rising edge on INT2 activates the interrupt. Edges on INT2 are registered asynchronously. Pulses on INT2 wider than the minimum pulse width given in Table 37 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. When changing the ISC2 bit, an interrupt can occur. Therefore, it is recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR Register. Then, the ISC2 bit can be changed. Finally, the INT2 Interrupt Flag should be cleared by writing a logical one to its Interrupt Flag bit (INTF2) in the GIFR Register before the interrupt is re-enabled. General Interrupt Control Register – GICR • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU General Control Register (MCUCR) define whether the external interrupt is activated on the rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. Table 36. Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request. Bit 765 4321 0 –ISC2 – – WDRF BORF EXTRF PORF MCUCSR Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 See Bit Description Table 37. Asynchronous External Interrupt Characteristics Symbol Parameter Min Typ Max Units tINT Minimum pulse width for asynchronous external interrupt 50 ns Bit 7 654 32 10 INT1 INT0 INT2 – – – IVSEL IVCE GICR Read/Write R/W R/W R/W R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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Descrição semelhante - ATMEGA8535-16AC |
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