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AM29BDS640GBC9WSI Folha de dados(PDF) 6 Page - Advanced Micro Devices |
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AM29BDS640GBC9WSI Folha de dados(HTML) 6 Page - Advanced Micro Devices |
6 / 77 page 4Am29BDS640G 25903C2 May 9, 2006 Preliminary Table of Contents Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .9 Special Handling Instructions for FBGA Package .......................... 9 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 10 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 11 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 12 Table 1. Device Bus Operations ...........................................12 Enhanced VersatileIO™ (VIO) Control ............................................12 Requirements for Asynchronous Read Operation (Non-Burst) ........................................................................ 12 Requirements for Synchronous (Burst) Read Operation ......... 13 8-, 16-, and 32-Word Linear Burst with Wrap Around ............. 14 Table 2. Burst Address Groups ............................................14 Burst Mode Configuration Register ................................................. 14 Reduced Wait-State Handshaking Option ..................................... 14 Simultaneous Read/Write Operations with Zero Latency ....... 15 Writing Commands/Command Sequences ................................... 15 Accelerated Program Operation ...................................................... 15 Autoselect Functions ............................................................................ 16 Standby Mode ......................................................................................... 16 Automatic Sleep Mode ......................................................................... 16 RESET#: Hardware Reset Input ........................................................ 16 Output Disable Mode ........................................................................... 17 Hardware Data Protection ................................................................. 17 Write Protect (WP#) ........................................................................... 17 Low VCC Write Inhibit ........................................................................ 17 Write Pulse “Glitch” Protection .......................................................18 Logical Inhibit ..........................................................................................18 Power-Up Write Inhibit ......................................................................18 VCC and VIO Power-up And Power-down Sequencing .............18 Common Flash Memory Interface (CFI) . . . . . . . 18 Table 3. CFI Query Identification String ...............................19 System Interface String..................................................... 19 Table 5. Device Geometry Definition......................................... 20 Table 6. Primary Vendor-Specific Extended Query .................21 Table 7. Sector Address Table .............................................22 Command Definitions . . . . . . . . . . . . . . . . . . . . . .26 Reading Array Data ............................................................................. 26 Set Burst Mode Configuration Register Command Sequence 26 Figure 1. Synchronous/Asynchronous State Diagram ............. 27 Read Mode Setting ............................................................................... 27 Programmable Wait State Configuration ...................................... 27 Table 8. Programmable Wait State Settings ..........................28 Reduced Wait-State Handshaking Option ....................................28 Table 9. Initial Access Cycles vs. Frequency ..........................28 Standard Handshaking Operation ................................................... 29 Table 10. Wait States for Standard Handshaking ...................29 Burst Read Mode Configuration ...................................................... 29 Table 11. Burst Read Mode Settings ....................................29 Burst Active Clock Edge Configuration ......................................... 29 RDY Configuration .............................................................................. 30 Configuration Register ........................................................................ 30 Table 12. Burst Mode Configuration Register ........................ 30 Sector Lock/Unlock Command Sequence .................................... 30 Reset Command .....................................................................................31 Autoselect Command Sequence .......................................................31 Program Command Sequence ...........................................................32 Unlock Bypass Command Sequence ...............................................32 Figure 2. Erase Operation.................................................. 33 Chip Erase Command Sequence ......................................................34 Sector Erase Command Sequence ...................................................34 Erase Suspend/Erase Resume Commands .....................................35 Figure 3. Program Operation.............................................. 36 Command Definitions .......................................................................... 37 Table 13. Command Definitions .......................................... 37 Write Operation Status . . . . . . . . . . . . . . . . . . . . 38 DQ7: Data# Polling ..............................................................................38 Figure 4. Data# Polling Algorithm....................................... 39 RDY: Ready .............................................................................................40 DQ6: Toggle Bit I ................................................................................. 40 Figure 5. Toggle Bit Algorithm............................................ 41 DQ2: Toggle Bit II ................................................................................. 41 Table 14. DQ6 and DQ2 Indications .................................... 42 Reading Toggle Bits DQ6/DQ2 ....................................................... 42 DQ5: Exceeded Timing Limits .......................................................... 42 DQ3: Sector Erase Timer ...................................................................43 Table 15. Write Operation Status ........................................ 43 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 44 Figure 6. Maximum Negative Overshoot Waveform ............... 44 Figure 7. Maximum Positive Overshoot Waveform ........................................................ 44 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 45 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 8. Test Setup ......................................................... 46 Table 16. Test Specifications .............................................. 46 Key to Switching Waveforms . . . . . . . . . . . . . . . . 46 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . 46 Figure 9. Input Waveforms and Measurement Levels............. 46 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 10. VCC and VIO Power-up Diagram........................... 47 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 48 Synchronous/Burst Read .................................................................... 48 Figure 11. CLK Synchronous Burst Mode Read (rising active CLK)............................................................ 49 Figure 12. CLK Synchronous Burst Mode Read (Falling Active Clock) ........................................................ 50 Figure 13. Synchronous Burst Mode Read............................ 51 Figure 14. 8-word Linear Burst with Wrap Around................. 51 Figure 15. Burst with RDY Set One Cycle Before Data............ 52 Figure 16. Reduced Wait-State Handshaking Burst Mode Read Starting at an Even Address .............................. 53 Figure 17. Reduced Wait-State Handshaking Burst Mode Read Starting at an Odd Address................................................ 54 Asynchronous Read ..............................................................................55 Figure 18. Asynchronous Mode Read with Latched Addresses . 55 Figure 19. Asynchronous Mode Read................................... 56 Figure 20. Reset Timings................................................... 57 Figure 21. Asynchronous Program Operation Timings ............ 59 |
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